Im working on the following question: enter image description here

I got the following answer is it correct? a) The total time = 10ns + 10ns +10ns = 30ns To calculate MIPS, divide one second by 30ns. MIPS = (1 x 10^9)/30 = 33,333,333.33ns

The maximum number of MIPS this machine is capable of in the absence of pipelining is 33.33 MIPS.

b) A Pipeline processor is comprised of a sequential, linear list of segments, where each segment performs one computational task or group of tasks.

The cycle time of the processor is reduced; increasing the instruction throughput. Pipelining doesn’t reduce the time it takes to complete an instruction; instead it increases the number of instructions that can be processed simultaneously and reduces the delay between completed instructions.

The more pipeline stages a processor has, the more instructions it can process at once and the less of a delay there is between completed instructions.

If pipelining is used, the CPU Arithmetic logic unit can be designed faster.

Pipelined CPUs generally work at a higher clock frequency than the RAM clock frequency, increasing computer’s overall performance.

Considering the overhead with pipeline be 2ns,then Clock time with pipeline = 10 + 2 = 12 ns. Assuming everything is neglected or included in overhead, with pipeline we complete 1 instruction every clock cycle. i.e.,

MIPS=10^(−6)/(12×10^(−9))=83.33 Speedup benefits=83-25=58 ns.

  • \$\begingroup\$ 1) To measure the impact of pipelining, you can't add other variables eg. clock speed. 2) The overhead depends on the code the processor is executing. If it does one ALU operation and then blocks (clears the pipeline) there's no benefit of pipelining, while if the processor is running an infinite sequence of ALU only instructions, it will (theoretically) be three times as fast. In reality, pipelining will make this processor 1 to 3 times as fast depending more or less strongly on what it's doing. \$\endgroup\$ – Oskar Skog Feb 5 '17 at 17:56
  • \$\begingroup\$ @user3472448 "speedup POSSIBLE" I would interpret that as maximum speedup possible, that would mean 10ns per instruction -> 100MIPS. Then the speed up benefit would be 100-33=67MIPS. \$\endgroup\$ – rioraxe Feb 6 '17 at 1:13

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