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Im working on the following question: Suppose an instruction can be carried out in 3 stages, the stages taking 3 ns, 7 ns, and 10 ns, respectively. (a) What is the maximum execution rate without pipelining? (b) What speedup is possible with pipelining?

I have managed to get the following answers is it correct? a) For a non-pipeline system these 3 stages can be carried out one after another. Total time required is (3+7+10)ns=20 ns Now to computer 100 instruction time required = 100*20=2000 ns

b) A very interesting feature of pipeline is that in pipeline all the stages have same length. In the given problem we have a stage, which takes 10 ns, which is largest. We will equate is value with the pipeline stages. So now each pipeline stage is of length 10 ns to execute. Now total latency time= 20*2 ns= 40 ns. There is an overhead associated with this. Lets assume overhead is of 2 ns. So total time to execute one stage of pipeline is 22 ns. Speed up is (3+7+10)/10=2.0

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  • \$\begingroup\$ What is the question? You have made a statement - are you asking if the statement is valid? \$\endgroup\$ – Peter Smith Feb 5 '17 at 17:18
  • \$\begingroup\$ @PeterSmith Im just checking if the answers I have come up with is correct. \$\endgroup\$ – user3472448 Feb 5 '17 at 17:20
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You got the right answer — 2× speedup, ignoring overhead — but through a completely invalid method. It's interesting that you introduced the concept of overhead, but ignored it anyway in your final answer.

The key concept that you're missing is that adding pipeline registers allows different parts of the pipeline to be working on different instructions in parallel. The latency for a single instruction increases slightly, but the number of instructions completed in a given amount of time scales with the clock frequency.

So, ignoring overhead for the moment, without pipelining, you need 20 ns to complete each instruction, for a throughput of 50 MIPS. Adding a pipeline register allows you to reduce the clock period to 10 ns, which increases the throughput to 100 MIPS, but the latency for each instruction remains at 20 ns. The speedup is a factor of 100 MIPS / 50 MIPS = 2.0.

Now, if a register adds 2 ns of overhead, this affects both calculations. Remember that there is an implied register even in the single-stage pipeline. Therefore, the clock period in that case will need to be 22 ns, giving a throughput of 45.45 MIPS. With the two-stage pipeline, the clock period becomes 12 ns, for a throughput of 83.33 MIPS, but now the latency for a single instruction is 2 × 12 ns = 24 ns. The speedup is a factor of 83.33 MIPS / 45.45 MIPS = 1.833.

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