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Im working on the following question: A computer with an 11-stage pipeline deals with conditional branches by stalling for the next 9 cycles after hitting one. How much does stalling hurt the performance if 10 percent of all instructions are conditional branches? Ignore all sources of stalling except conditional branches.

I got the following answer is it correct? enter image description here

Is it correct?

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  • \$\begingroup\$ "1 out of 5" - are you sure? \$\endgroup\$ – Tom Carpenter Feb 5 '17 at 18:17
  • \$\begingroup\$ is it 1 out 10? @TomCarpenter \$\endgroup\$ – user3472448 Feb 5 '17 at 18:25
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I interpret the question this way: 10% of the instructions require 10 clocks each, while the other 90% require 1 clock each. What is the average number of clocks per instruction?

The total length of the pipeline is what is known as a "red herring" — information that isn't actually needed to answer the question.

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In a pipelined architecture instructions are processed in small parts, with one part being processed each clock cycle. Assuming no stalling, one instruction completes its last stage every clock cycle. So with no stalls 10 instructions would complete in 10 cycles (and in this case 11 more would be partially processed in prior pipeline stages).

If 1 out of 10 instructions stalls for 9 cycles then the total time for 10 instructions to complete is... 10 clock cycles + 9 stall cycles = 19 cycles.

So the overall performance is 10/19 = 52% of what it would be if no stalls occurred.

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  • \$\begingroup\$ We generally do not give direct answers to "homework" questions. Instead, we try to guide the OP into discovering the answer on their own. It's the difference between "giving a man a fish" and "teaching a man to fish". \$\endgroup\$ – Dave Tweed Feb 5 '17 at 20:58

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