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I am trying to build a laser diode driver circuit using a part from Analog Devices. (The datasheet is here for your reference: http://www.autex.spb.su/ad/ADN2848.pdf)

It appears that there are 4 data inputs: DATAP, DATAN, CLKP, and CLKN. There also appears to be a clock select (CLKSEL) pin. I am relatively new to this sort of thing, so I'm not exactly sure how to interpret the data sheet to figure out what communication protocol to use when inputting data. Does anyone know what the protocol is, or have any thoughts/advice if not?

I also notice that the data sheet gives two values relevant to the data inputs: t setup and t hold. Are these relevant to the communication protocol that needs to be used?

Thank you!

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  • \$\begingroup\$ The datasheet clearly states that these are DIFFERENTIAL inputs, 100 Ohm terminated, DATA and CLOCK. I would suggest to find application notes for this device, they will likely provide more ideas on how this driver is used. This is for ultra-high speed Sonet protocols over fiber optics. What are you trying to use it for? \$\endgroup\$ – Ale..chenski Feb 5 '17 at 21:51
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There are differential inputs (CLKP is the positive phase, CLKN is the negative phase). Differential signals are often used in high-speed circuits, for improved noise immunity and reduced signal swing.

The setup and hold values are the timing requirements between clock and data. This has nothing to do with protocol, just when the data needs to be stable around the active clock edge.

This driver is totally protocol-independent. It merely turns a serial bitstream into drive levels for the laser. Protocol happens way upstream.

I suspect you've got some serious studying ahead before you can get this to work...

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It looks like it's just a flip-flop with differential inputs.

Each signal is considered high when 'P' > 'N' and low otherwise. The device updates 'data' on the rising edge of the clock. The setup time is the minimum time period that data must be stable before that rising edge, and the hold time is the minimum time it must be kept stable after the edge.

CLKSEL allows you to bypass this. If CLKSEL is high, clocking is used. If it's low, it looks like data just goes directly to the diode.

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Well the part is clearly set up for AC coupled LVDS or maybe PECL logic, and obviously the line rate will have to satisfy the setup and hold times relative to the clock edge if the clocked mode is in use.

The fact that the AC coupling is required means that you will need to use some line coding in all probability, 8b10 or such to avoid large DC shifts, do not do what SDI for example does and end up with pathologicals with long sequences of 1 or 0, it causes DC shifts in both the line RX and the ALC loop as well as making clock recovery a pain.

Apart from that the thing is completely protocol independent, it is up to you what bit patterns you send it.

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I would usually expect to drive this type of device from an LVDS (Low Voltage Differential Signaling) output from a device such as an FPGA or ASIC for SONET etc Overview of LVDS.

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