Have you plotted the stability circles? Do a load pull and plot these, they contain useful information.
Low frequency instability is often down to one of a few things:
Source impedance goes high Z at low frequency, unterminating the input: Either provide a low frequency termination or an input pad of a few dB or so to reduce the mismatch at the input. A capacitvely coupled input is a common gotcha here.
Power rail resonances, the DC injection choke can end up resonating with the supply capacitance in the audio or low ultrasonic region where LDMOS has gain for days. Adding some resistive losses helps (Either a resistor of a few ohms across a suitable inductor or in series with a modest electrolytic, this sometimes shows up as squegging).
These sorts of parts have HUGE gain at low frequency, and often a 10n cap and few hundred ohms of series resistor from each drain to the corresponding gate will help to tame this beast, you can use a little inductance here if it helps to reduce the effect of this network at VHF and up where the gain is actually useful.
Is this a swamped gate or tuned gate design?
Circuit diagrams, intended operating band and layouts would all be helpful for diagnosing this.
Having now seen the layout, there is no resistive load on the gates at all when the input is disconnected, with 30-40+dB of power gain down there, of course it oscillates.
Start by adding a few tens of ohms in a large SMT package directly between the gates, it will reduce the gain but improve the stability, 15 ohms or so is a good starting point.
What frequency is the thing going off at? If the problem is a low frequency oscillation then a few tens of nF in series with maybe 500 ohms between each drain and the corresponding gate will help to tame the very large LF gain, but start with that gate swamping resistor.