Using 3 cascaded C-FB-C filter circuits, the C-FB-C placed in ALL the VDDs and RTN, and with +15/-15/+6/-6/+5/RTN filtered at the switcher-supplies+DSP / centralClockGen / signalchain we used 6 * 3 = 18 of the C-FB-C circuits, I achieved 15 bit noise-floors at 6Million conversions per second. The floor was 150 microVolts. The sensor was a focal-plane IR sensor, itself isolated from ground with 100micron glass beads in the epoxy, thus 50 pF capacitance from the sensor to the chassis/airplane. In the sensor head, I used 10 ohm resistors into each opamp, plus 0.1uF and 10uF, to ensure all the fast signal-related current-surges were provided locally; thus none of the OpAmps were able to interact, via VDD, with any of the other OpAmps. In other words, VDDs went thru a low-pass-filter to enter any of the signal chain opamps. [concept: have 'local batteries']
simulate this circuit – Schematic created using CircuitLab
For ultimate noise/crosstalk_between_ICs, people use a VDD_Tree, to locally implement private_filtering of VDD for each IC. With the power supply rejection at DC often being 80 or 100 dB (thus 60Hz is rejected by 10,000 or 100,000) but becoming much less at high frequencies, you need to implement low-pass-filters in the VDD, with corner frequencies of 100Hz or so. Thus 100 ohms and 10uF, providing 1milliSec tau and 159Hz corner, is good. Or 10 ohms and 100uF. The typical VDD tree is shown in the final diagram of this answer.
I've read about Shunt Regulators for 1 nanoVolt noise levels, for audio vinyl RIAA playback PreAmps. Their PreAmp has no NO power supply rejection, and a low noise ShuntReg has been key to extremely pleasing music. That discussion is at "Simplistic NJFET RIAA" thread, on 'diyAudio' website. Again, that is for 1 nanoVolt levels, in my opinion; the audio experimentors just savor the music, they don't try to compute the VDD ripple floor.
You can easily model the Power Supply rejection of the OpAmps in your circuit, using individual models or Global models, using the tool Signal Chain Explorer.
You describe the PSRR as [DC_attenuation, Frequency_corner where attenuation begins to lessen]; you also have RL-C-R-CCC filter networks customizable for each OpAmp; ESR and ESL are params for each capacitor. This tool is free, from robustcircuitdesign.com If you download and use it, feel free to tell us how convenient you find the menus.
Here is the VDD menu for one opamp; click "power" button after selecting stage.
The various capacitors in parallel are used to show the series + parallel resonance dips and peaks of poorly-designed VDD filtering.
Here is "SHOW FILTER RESPONSE" of the default-values LRC-RCCC network (without PSRR).
Observe the resonance of 10nF & 1uF (with their ESLs) at 26MHz, where opamps exhibit 0DB PSRR. Dampening is needed.
Some years back I needed a gain of 1Million at 100,000Hz for a magnetic-beacon prototype. Input was 2uVpp, output was 2 voltspp. I wanted to switch the gain, in binary steps, to keep the ADC signal between -6db and -12dB FullSwing, to tolerate thermal noise.
Major risk was oscillation, with the VDD-tree providing the feedback path; given OpAmp PowerSupplyRejection is poor (if not zerodB) at 100,000Hz, I knew VDD distribution was necessary design task. As teenager, I built numerous audio high-gain amplifiers that almost always "motorboated" puuut-puuut-puuut as the stages were driven (by themselves) from min-out to max-out. Here is the first-pass successful VDD-tree.
Each of the GNDs shown is separate from the other GNDs,
probably by several centimeters,
to minimize coupling. Notice the LPF, 10 Ohm & 1,000uF, is 16Hz.
simulate this circuit