# Computer clock technology?

Let's say I have a computer running at 4 GHz.

I would say it means I need a way to measure increments of time of about 0.25 ns.

How does a computer do that? My question is both:

• Technological: what is the "physical" technology of the raw sensor (is it quartz? What are its defining characteristics ?)

• Practical: based on this raw sensor, what methods are put in place to actually be able to measure such a small increment of time somewhat correctly? E.g. if you tell me the clock uses a quartz whose frequency is about 32768 Hz, how do you use that to measure a 0.25ns increment? Do you amplify the quartz signal so massively that you can actually measure a 0.001% variation of amplitude in the resulting signal? in which case, what about noise in the amplification procedure?

• Go look up "Clock multiplier" and "Phase Locked Loops" Feb 6, 2017 at 13:55
• see all the great answers on PLLs. But they are missing the point that (for your 4GHz computer) it is difficult (but possible) to have external signals at that speed. But internally not as much of a problem. So the reference clocks are relatively slow 100mhz usually but for some reason RTCs often use 32768, on die you can multiply the ref clocks up with a PLL. Giving a timer with more resolution (but some jitter). Feb 6, 2017 at 16:04
• @old_timer RTCs use 32768 Hz for a very good reason. That way your divider to get to 1Hz is an exact power of two. Feb 6, 2017 at 17:32
• @old_timer, also, 32768 Hz crystals and circuits are cheap as dirt and extremely low power because that's the technology that's used in all of the quartz watches in the world. Feb 6, 2017 at 17:51

It's not a "sensor", it's a generator; time is not a thing that can be directly sensed. See How does a quartz crystal work?

The crystal does not itself produce the 4GHz signal, that's done with a PLL (as in pgvoorhees' comment): For a PLL Clock multiplier, where does the new clock come from?

Basically, there is a tuning process. A free-running voltage-controlled oscillator (VCO) is set up to run at "about" 4Gz. Its output is fed into a counter. Every tick of the lower frequency crystal, a comparison is made to see if the VCO is "fast" or "slow". For example, with a 4MHz reference crystal, you'd expect to count 1000 VCO clocks for every crystal clock. If the count is e.g. 1057, then the VCO is slowed down a bit.

what about noise in the amplification procedure

The key quality of a PLL clock is "jitter" - small variations in the timing. They're designed to bring this within specified levels. However, sometimes a modulation is deliberately applied ("spread spectrum") to vary the clock frequency by sub-percent amounts. This makes it easier to pass EMI tests.

Remember that 0.25ns = 250ps, which is (necessarily if your computer is to be useful) many times the delay of an individual gate, which may be in the 1-10ps range.

Note also that the clock frequency can often be adjusted at runtime to save power: How can a CPU dynamically change its clock frequency?

• Not only that, but the clock frequency can be set within a range based on external factors (E.g.: temperature, power input, ...) or even by software (opening a demanding game/application, CPU over/underclocking in the O.S., Windows lowering the CPU speed to cool it down, ...). Feb 6, 2017 at 16:23
• +1 for saying "makes it easier to pass EMI tests" instead of "reduces EMI". Feb 7, 2017 at 3:21
• Yeah, of course time isn't sensed by itself, but whatever. It was a figure of speech. Thanks for the answer. Feb 12, 2017 at 19:43

There's several ways to generate a fixed frequency. Quartz crystals are one, which use mechanical resonance to generate a fixed frequency. There's other types of mechanical resonators as well, ceramic oscillators come to mind, and there's also other ways to achieve resonance and/or oscillation. Anyway, mechanical resonators can be very precise, with precision measured in parts-per-million. They don't go far above 100 MHz though. Perhaps even more importantly though, their frequency is fixed, while computers can change their clock frequency at run-time, for instance for throttling based on frequency or power source, or just to satisfy overclockers.

It is also possible to generate frequencies by stringing purely electrical components together in such a way that they oscillate. Without going into detail about all the ways you can do this, the typical way that I know of that can generate high frequencies such as these is stringing an odd amount of inverters together. There's no stable state, so this will oscillate as fast as the inverters will go. A nice feature here is that if you change the operating voltage or some other characteristic of the inverters a little, the frequency will change. Such a thing is called a voltage-controlled oscillator, or VCO (this is a broader term though, there's more ways to make a VCO; here's an example of a device using the method I'm referring to). A downside is that due to the IC manufacturing process you don't really know what the frequency will be, and it will differ greatly between devices, based on temperature, age, etc..

These two technologies can be combined. The basic idea is that we can measure the frequency coming out of the VCO using a reference frequency from a quartz crystal, and then adjust the control voltage of the VCO to make change it to the frequency we want. This can be accomplished using a phase-locked loop (PLL). Specifically, a PLL tries to make its feedback input frequency and phase exactly the same as its reference input. So what's the point of generating something that's exactly the same? You can put any kind of circuit you want between the VCO and the PLL feedback input, in this case most notably a frequency divider. Frequency dividers are easy, you just make a counter that always increments until it reaches a set value, at which point it resets and toggles the state of the output clock. The PLL will try to make the output of the divider the same as the reference clock, therefore the output of the VCO must be the reference clock times the divider value, and we're done.

If you're mind-boggled about how inverters can be fast enough to generate such small time periods, consider that to make a processor you actually need to be able to compute things between two clock edges. (If you did not know/realize this and want to learn more, "synchronous logic" would be a good search term.) That computation is a lot more than a couple inversions, so VCOs will always be able to synthesize frequencies that are useful as a clock. In fact, the VCO might run at 10+ GHz, with the actual processor clock divided down from there, in order to be able to synthesize more frequencies, or just because it saves inverters in the inverter chain. I'm currently working in a group that is developing an IC based on a 60nm technology (much older than what's used in your computer) and if I recall correctly, the latency of an inverter is in the order of 0.1ns.

There are two clock sources. A silicon voltage controlled oscillator (VCO) at roughly the correct frequency but with terrible accuracy and a reasonably accurate quartz crystal, normally in the 25-50 MHz range.
The output of the VCO is divided down so that it's nominal frequency is the same as the quartz crystal (e.g. 4GHz / 128 = 31.25MHz) and the two are compared. The output of that comparison is fed into the control input of the VCO to control the speed of its output.

The end result is that once things have stabilized (which can take a while) the VCO output will be an exact multiple of the quartz input.

This setup is called a Phase Lock Loop or PLL, this is only a very simplistic explanation of how they work, as with many things the complexity is in the details. Google PLL for far more detail and then ask again if you have specific questions.

• While not frequencies but exact phase are compared, still +1 especially since you tagged it as a simplistic explanation. Feb 6, 2017 at 17:17