In the circuit below, it seems that the JFET is biased in a regime with very low current (pinched off?).

With respect to most designs I came across, this one uses rather large source and drain resistors (factor 10 more than usual). I think it is pinched off by this biasing (datasheet gives cutoff voltage of \$V_{gs}=-1.1V\$ with \$I_d=10\mu A\$).

  • What are the advantages? (Why is it used rarely? It is a rare configuration, isn't it?)
  • How can one calculate operating point and amplification factor from data sheet parameters?

I understand that in pinch off, the drain current is exponentially dependent on \$V_{gs}\$, i.e. \$I_d(V_{gs})=I_0\exp\left(\frac{V_{gs}}{n\cdot k_B T/q}\right)\$. But, I never find \$n\$ mentioned in the data sheets. Also most SPICE models seem to fix it to 1. Is this okay? I heard somewhere that it can vary from 1 to 3ish.


simulate this circuit – Schematic created using CircuitLab

(The schematic is adapted from schematics of a lightgun that I found on the web. D1 could also be a phototransistor or forward biased, but I don't think this matters!?)

[Question edited after discussion with FakeMoustache below.]

  • 1
    \$\begingroup\$ JFET in weak inversion/sub-threshold regime. As far as I know weak inversion / sub threshold is for MOSFETs. This is a JFET. JFETs are mostly depletion type so normally ON when Vgs = 0. In this circuit the JFET is biased such that Vgs is slightly negative which is a very normal mode of operation for a JFET. \$\endgroup\$ Commented Feb 6, 2017 at 22:00
  • \$\begingroup\$ @FakeMoustache: What makes me believe it is sub threshold (which AFIR exists for all FET types, but just starts at more negative Vgs for JFETs) is the large resistor values of Rs and Rd. Essentially, max. 10uA (DC) flow. Normally, I see resistor values of 1 to 10k in similar circuits. \$\endgroup\$
    – magnustron
    Commented Feb 6, 2017 at 22:18
  • \$\begingroup\$ The difference between weak and strong inversion in MOSFET is in the value of Vgs, it has nothing to do with the resulting Id \$\endgroup\$ Commented Feb 6, 2017 at 22:21
  • \$\begingroup\$ Aren't the two interrelated in this circuit due to the feedback caused by Rs? The 2SK104 has a typical cutoff voltage of Vgs=-1.1V, with Id=10uA datasheet. \$\endgroup\$
    – magnustron
    Commented Feb 6, 2017 at 22:41
  • \$\begingroup\$ No, lookup what an inversion layer is. It applies to a MOS structure. This is a JFET, it does not have a MOS structure, it has a PN junction which is ”pinched” by the gate's depletion layer. JFETs do not have inversion let alone weak or strong inversion. Again: look up what inversion means and notice how it needs a MOS structure. \$\endgroup\$ Commented Feb 7, 2017 at 7:41


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