# Tolerating Logic Inputs in Excess of Vcc

Referencing this TI inverter as an example part: http://www.ti.com/lit/ds/symlink/sn74ac14.pdf

Specifically, the table at the bottom of page 2 (I would put a picture but I do not know where to upload it). It lists the max Vcc as 6V. It also says the voltage input range is -0.5V to Vcc+0.5V. There is also a note 1 which says "The input and output voltage ratings may be exceeded if the input and output current ratings are observed."

I want to use a Vcc of 3.3V, but I have one input that would be 5V. TI has other inverters that allow 5V inputs with 3.3V Vcc, but their input leakage current is too high for my other inputs. Therefore I am interested in exploring this note.

What does it mean when it says "if the input current rating is observed"? Would this be the input clamp current, Iik (+/- 20 mA)? If so, does that mean I need to put a series resistor in front of the input, so that e.g. 5V - 3.3V = 1.7V (EDIT: and subtract diode drop 0.5V = 1.2V) dropped over the series resistor induces Iik < 20 mA? Should I be concerned about this series resistor being too large, such that the induced current would be less than the input current Ii = +/- 1 uA max?

This question is slightly related to another question on this stackexchange ( Why is it important not to exceed Vcc at the input to a logic gate? ), where one answer off-handedly mentions using resistors to limit input currents, but I would like more detail using a concrete example, especially since this datasheet implies that it's possible to do safely.

Note extremely carefully that note 1 that you refer to in th data sheet applies to the absolute maximum stress only ratings table above the note.
Note that the table below note MUST be what you use for ormal operation.
The normal operation table says that input and output voltgaes both have lower and upper limits of 0V (ground) and vcc respectively during normal operation.

If you violate the spec sheet normal operating conditions requirements you can expect to experience abnormal operating conditions. These may range fro perfectly normal opration through complete maloperation in all cases through to the worst case on unpredicatble possibly unnoticed until something really critical depends on it mis-operation. This can include dying, caching fire or doing anything at all that is not against the laws of Physics under the given circumstances.

The Sparkfun tutorial is generally good but contains one horrendously bad piece of advice,

The Sparkfun resistor and diode solution is safe but pulldown or low is to about 0.6V and pullup is slow compared to a gate switching as the 10k resistor must charge gate an stray input capacitance. These effects often will not matter.

The Sparkfun MOSFET solution is excellent - although the MOSFET used is somewhat marginal at 3V3 gate voltage.

The Sparkfun series 10k resistors in each line is an invitation to disaster and random problems forever.

DON'T DO IT !!!!

To maintain the IC in spec sheet limits Vin <= 3V3 so current flow in the 10k resistor = V/R = (5V- 3v3)/10k = 170 microamps.
170 uA is not very much in most normal circumstances + here it is very likely to drive the pin above 3V3. Catch diode conduction begins reasonably noticeably at about 3.8V and is in full swing by 4V. At 4V you can expect about (5-4)/10k = 100 uA. This current will often be injected in the substrate of the IC in places it was never designed to go and can cause parasitic transistor or can latch nodes in existing devices by inpecting charge that cannot dissipate into floating nodes

MANY people argue violently against the above. They say that it is OK to violate spec sheet limits and to inject current into places that it does not belong and that such actions are consistent with good engineering practice. Walk away lowly from such people with your hands in sight.

I may have not been clear enough in what I was trying to say.
The table in the datasheet at the bottom of page 2 is headed
"Recommended operating conditions (see Note 3)".
ABOVE the table are notes 1 & 2 BUT they are referenced ONLY in the table above them in mid page headed
"absolute maximum ratings over operating free-air temperature range (unless otherwise noted)".

ie down to the end of note 2 relates to IC survival worst case.
BELOW note 2 relates to IC operation. Nothing in note 2, and above says the IC will OPERATE NORMALLY. Just that it will survive.

Note that this is NOT pedantry - this is how the data sheet is intended to be read but it is not always 100% clear when it is all presented together. Datahseets essentially always start with an abs max survival section and then follow with a recommended section. "Recommended" has min & max values for various parameters and transgressing them means you cannot guarantee correct operation.

In the case of protection diode currents

• 10 mA will almost garantee disaster and 1 uA will almost guarantee no observable problems.

• At 1 mA and 10 uA you are likely in trouble and likely OK.

• At 100 uA and 100 UA (ie they meet) you are in a grey area and anything may happen and sometimes does. It can be random, intermittent and project and sometimes product destroying. Occasionally may be life destroying.

Good engineering and Murphy say that you do not go outside spec sheet min-max range.

• I would hope the IC was designed so current from a clamping diode doesn't get injected randomly into the body. And the heading says "Abs Max (unless otherwise noted)", so the note leads me to believe that the actual max is excessive Iik for this particular IC. However, you are correct in that you cannot just rely on this without a noted exception. Any potential replacement chip would have to be able to withstand the exact same conditions. Mar 22, 2012 at 15:29
• @ajs410 - You can hope :-). In fact some aspects related to this are designed against in modern ICs. One result is a conditiin called "SCR latchup" where the diode conduction triggers-on a parasitic SCR across the supply. Magic and other smoke can occur and IC destructiin was not uncommon. People have for many years designed in guard rings and other forms of protection to minimise this effect. But that is because the abs max condition is meant to not causeIC destruction. Protection against maloperatioj is less needed as you just set limits that are safe and people don't exceed them. Right ?:-) Mar 22, 2012 at 15:48
• Alas, a genration or two have grown up who do not know what "asolute maximum" and "operating" mean, and they will argue at any length to justify what is manifestly really bad and unjustifiable engineering practices. Alas alas a few of these work for IC suppliers and write application notes :-(. These are NOT the IC designers and they can and do put out some utter rubbish on occasion. Caveat emptor etc. Mar 22, 2012 at 15:50
• I am not trying to argue at length with you, just pointing out that the datasheet (not an app note) itself says "Absolute Maximum ratings (unless otherwise noted)", and that it is in fact noted. My question really comes down to "is the input current it's talking about Iik?" Mar 22, 2012 at 16:13
• @RussellMcMahon: That probably stems from the fact that many data sheets are written with a huge gap between their page-one advertised features and their defined operating characteristics. If a device claims on page 1 that its pins can source or sink 20mA, and the absolute maximum ratings page gives per-current pin as 20mA, and the only thing Recommended Operating Conditions has to say is that VOL will be 0.5V at 4mA, should an engineer figure or not figure that it should be safe to drive an LED through a resistor that would pass 15mA if the output was grounded to 0V? Mar 22, 2012 at 17:14

The specification means that, provided VDD is kept within bounds and other limits are exceeded, one may source or sink 20mA from any I/O pin without pulling it far enough to damage the part, and one may connect any I/O pin to a rigid voltage between -0.5V and VCC+0.5V without driving enough current through the clamp diodes to damage the part. Note that the only guarantees with regard to pulling an I/O pin beyond the rails are those stated above. In particular, there is no guarantee in the data sheet that pulling a pin even one millivolt beyond the rails won't disrupt the operation of the part--merely that it won't cause permanent damage.

• +1 for mentioning the difference between 'won't cause permanent damage" and "won't disrupt the operation of the part". Mar 23, 2012 at 2:55

This is a nice tutorial on the matter from SparkFun. A 10K resistor between the 5V output and 3.3V input limits the current to something harmless. This only works if your IC has input protection diodes to the rail. Since the "normal" current for CMOS logic is 0, you don't need to worry about your resistor value being too large unless it is so large that the gate capacitance becomes a limiting factor.

The current in question flows from the 5V output, through the series resistor, through the protection diode on the 3.3V pin, and to the 3.3V rail. If your voltage regulator cannot handle reverse current (common) then you should put a shunt resistor between 3V3 and GND to carry away the current.

The neat thing about this method is that it doesn't always work. According to Xilinx, it's OK for their "Spartan 3 and 3E devices with both power and ground diodes" but not for Extended Spartan 3A FPGAs.

• Does the current flow from 5V rail to 3.3V rail imply that my 3.3V regulator would need to be capable of handling reverse current protection? Mar 21, 2012 at 20:19
• You need to make sure the 3.3V rail will be able to sink the current. Usually, you have other components drawing current from the rail, so it isn't a problem, but some low power circuits draw almost nothing from the rail. You could always add a resistor load to the rail, or a zener diode or something. Mar 21, 2012 at 21:38
• I've just given this my first ever vote-down - Sorry :-(. I'm afraid this is horrendously bad advice. Please see my answer to see why. It is bad engineering to exceed data sheet normal operting condition limits (does ANYONE here disagree with that statement?) and the datasheet says Vin MUST be between 0V and Vcc during normal operation. in may exceed 0-Vcc by up to 0.6V ONLY when absolute maximum limits are being dealt with. Mar 22, 2012 at 5:15
• @markrages I vaguely remembered something from an FPGA datasheet once that talked about this reverse current. Your comment makes sense; so long as there's enough load to sink the reverse current you're okay, because the regulator will just source less current to compensate. But you cannot have so much reverse current that the regulator would need to sink current to compensate, unless its specially designed to do so. Mar 22, 2012 at 15:33
• @RussellMcMahon I appreciate your concern, but Xilinx says it's OK for certain devices. Clearly the trick is to determine whether or not you have those devices. Or he could just use a resistor voltage divider. Mar 22, 2012 at 16:45