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As a student, when I needed to make a PCB, I just placed the components & auto-routed on ARES, and they usually worked well. However, now a fresh graduate & novice engineer, I found that this method is not suitable for all designs.

I checked through some application notes on low EMI PCB design, like these:

PCB Design Guidelines For Reduced EMI - Texas Instruments

AVR186: Best Practices for the PCB Layout of Oscillators

I understood the logic behind the tips in the notes. However, I am having a hard time applying these, because when I try to comply to a tip, I am contradicting with some other...

To sum up, I kindly request steps necessary - perhaps a flow chart - for low EMI PCB design from a relatively more experienced designer than me.

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    \$\begingroup\$ Unfortunately, there are a lot of conflicting ideas out there. No flowchart. Maybe buy a book and follow the book. Basic idea is, provide low impedance return path for all high-speed signals. Understand where all high current flows will be located. High impedance analog inputs are most likely to become victim signals. Don't split ground planes. \$\endgroup\$ – mkeith Feb 7 '17 at 8:35
  • \$\begingroup\$ @mkeith Thanks for the tips. Most of the books are out of my budget range, USD/TRY parity too high... \$\endgroup\$ – C K Feb 7 '17 at 8:47
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    \$\begingroup\$ Check online for stuff by Howard Johnson, maybe. Read through old threads on this forum. \$\endgroup\$ – mkeith Feb 7 '17 at 8:59
  • \$\begingroup\$ Try to find example chapters for H.W. Ott's Electromagnetic Compatibility Engineering online. \$\endgroup\$ – CL. Feb 7 '17 at 9:36
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    \$\begingroup\$ There is a set of Howard Johnson videos available for free on the Oxford University continuing education site which are excellent. \$\endgroup\$ – user1844 Feb 7 '17 at 9:43
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The first thing is to realize that EMI\EMC is an art not a science, the goal is to eliminate noise (one man's noise is another man's signal) and to pass regulatory if necessary. There isn't a checklist, its really dependent on the design.

Why is it an art? because each design is different and even the smallest differences (in parasitics or other factors) can make a big difference on whether the design works or passes regulatory. One method of doing things might work great for one design but not for another. It is usually easier (and less time consuming) to test then to model, but applying the rules will help understand what needs to be done to solve the problem.

I'll go over the basics each could be a chapter, but things designers need to be aware of. If you don't recognize what they are then start doing some research on the topic. (This is not an all inclusive list, but I hope to hit most of the topics)

1) Parasitics. Every component has parasitic inductance, capacitance and resistance. Know what these are for each component and learn when the design needs to take them into account (Usually +50Mhz parasitics will come into play)

2) Common mode noise, voltage running through a common pathway (ground, cables) can create noise on two loads.

3) Return currents. The ground plane is not 0 ohms, it has parasitic resistance. Currents from devices return back to the source through the lowest impedance pathway

4) Mutual inductance PCB traces, cables (any conductor with current) has magnetic fields, these will couple to adjacent conductors.

5) Ground loops - don't create ground loops, there are many ways to do this.

6) Shielding, Shields stop electric fields (there is also magnetic shielding) Shielding can create its own problems if currents through shields are not accounted for (can cause ground loops and antennas)

7) Antennas, Everything functions like an antenna including traces, planes and cables. Find out when this will be a problem.

8) Split planes, for some designs it may be advantageous to split digital and analog planes, in others not.

9) Switching loads, whether it is a clocked\switching PCB trace, a DC to DC converter, a switching power supply or a PWM load. These will all generate copious amounts of noise on a wide range of frequencies. Impedance control will need to be implemented (remember that currents will take the lowest impedance pathway)

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If interference between aggressive signals and sensitive signals is part of your interest, such as high-slew-rate electric field trashing an analog signal, or a high-slew-rate magnetic field trashing an analog signal, then download and use Signal Chain Explorer, from robustcircuitdesign.com Build your signal chain (use menus on the left), click "Update" on the right and see your SNR.

Then click "gargoyles" and "update", to see how badly the default aggressors have reduced the SNR. The defaults include Hfields, Efields, VDD trash and GND currents; each of the 4 types provide small databases of examples you are free to turn on/off, or edit, or click "new" in a database to enter your own aggressor.

Summary: use a Ground Plane; place a bypass cap at VDD pin of every IC; do not share bypass caps; to prevent sharing, insert 10 Ohm resistors (for analog ICs) or ferriteBeads (for digital ICs) back to the bulk supply; do not share GND vias; do not slit the Ground Plane if you expect to have noisy traces over the slit, or if you expect to run sensitive traces over the slit; low resistance nodes are more robust against electric fields; tiny loops are more robust against magnetic fields; explore the "show interconnects" button, and try editing the "interconnect wiring model" for trace/twinlead/twistedpair/coax.

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  • \$\begingroup\$ If there is a power plane, you will get WAY better EMI performance by not putting series elements between the plane and the pin. Just connect everything to the plane with a via. Trace must be as short as possible. You still want to place bypass as close as possible to the pin, like you say. \$\endgroup\$ – mkeith Feb 9 '17 at 5:00

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