Why here http://www.talkingelectronics.com/projects/MOSFET/MOSFET.html they say that push-pull configuration with high-side transistor as PMOS and lowside as NMOS is incorrect?

I have found many sources which state that that configuration (PN) is correct like STM32F0 reference manual,GPIO section

Also the simulator shows both configurations (PN and NP) seem to work simulation

How it is correct?


2 Answers 2


The web page you linked to says:

When the input is at mid-rail, a voltage between gate and source will be produced for both MOSFETs. Since a MOSFET can handle many amps, this will put a short-circuit across the power rail and will cause a lot of damage.

This is true.

But the GPIO output FETs inside a chip do not allow many amps, so the resulting current is not as large and will not immediately blow up the chip. Furthermore, these small FETs have a very small gate capacitance, so the switching will happen very quickly and the current will not flow for a long time.

But it still happens. The resulting current fluctuations on the power supply lines are why you need decoupling capacitors for digital chips, and why the switching noise is usually worse for outputs with higher drive strength.

  • \$\begingroup\$ Thank you. I overlooked that part. For PN push-pull when driving the gates high, I get a short in simulations \$\endgroup\$
    – fjohn
    Feb 7, 2017 at 10:46
  • \$\begingroup\$ I have put this question because I have a GPIO pin in open-source mode with pull-down (aka wired-or). So i tried to figure what configuration is used for the pin output stage. I guess it is PN (P highside, N lowside) \$\endgroup\$
    – fjohn
    Feb 7, 2017 at 11:06
  • \$\begingroup\$ The upper transistor must be P; an N-channel transistor would require a gate voltage higher than VCC. \$\endgroup\$
    – CL.
    Feb 7, 2017 at 12:17

If you also plot the current through the mosfets you will see the difference. For low current mosfets it is fine to use the high side P-mos and low side N-mos and connect the gates together. This will still cause a short, but only for a very short amount of time. You will find that if you switch with a high frequency the mosfets get warm because they short more often and dissipate the power.

For big mosfets, the high gate capacitance makes a slow rise time, causing both transistors to be on for a longer time during the transition, shorting the supply to ground for a substantial time.

The solution for big (high current) mosfets or slow rise times is to use a non-overlapping gate driver. This means that one would first turn off one transistor and only when it is off, turn on the other transistor.

An example of a non overlapping gate driver and the output waveform is shown below.

enter image description here

  • \$\begingroup\$ you mean a dead-time insertion? \$\endgroup\$
    – fjohn
    Feb 7, 2017 at 10:45
  • \$\begingroup\$ you could call it a dead time. Its just a short time to prevent the transistors from both being on at the same time during transition... \$\endgroup\$
    – Douwe66
    Feb 7, 2017 at 10:57

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.