0
\$\begingroup\$

I'm trying to drive a Telit UL865 UART 1.8V input with a ATMega32u4 UART 5.0V output. Both of these gates are CMOS. The datasheet for the Telit says that it has a 5K to 12K pullup on the input. I believe that I need a voltage divider to drop the 5 to 1.8, but I can't tell if the pullup resistor is on the gate side of the CMOS or the source/drain side. I imagine that if its on the gate side, the voltage divider will be thrown off by pull up resistor that is parallel to R1. Where would the pull up resistor be placed in a discrete schematic of a CMOS gate?

\$\endgroup\$
0

3 Answers 3

0
\$\begingroup\$

If they are stating there is a pull-up, they mean it is right at the input pin, so yes, it would affect your resistor divider design and you would want to account for that. Ideally a level-shifter would be used, but I've done it with a resistor divider also and it should work OK. Be careful about baud rate, because you may not get full bandwidth with a resistor divider as you would with a level-shifter. The other downside to using resistors is that it will be less efficient. If that's not a concern then OK.

So pick two resistors such that they produce a voltage less than 1.8 and above the max turn-on voltage for the input pin, when considering the internal pull-up. When you account for the pull-up, you can't just consider it as parallel with the external top resistor though, because they would be tied to different rails.

Actually, if you ignore the internal resistor, as long as your external resistor divider produces a value less than 1.8V, it will still not exceed 1.8V when the internal pull-up is added. Then you just need to be sure that the external resistors are low value enough that when the UART line is low, that the internal pull-up is brought low enough to be seen as a logic 0. It complicates the design a little. It's definitely better to use some level shifting logic.

\$\endgroup\$
1
\$\begingroup\$

The pullup is from the input to the 1.8V supply.

schematic

simulate this circuit – Schematic created using CircuitLab

It would be better to use either a specific level shifter chip (the kind with two supply pins) or a transistor rather than a voltage divider. The maximum '0' input level is only 350mV not accounting for any noise margin. If you pick 200mV as the output voltage that is acceptable for the output you need less than 625\$\Omega\$ for the lower resistance, so a fair bit of current from the AVR, but probably okay (1.1K + 620 maybe, but check how close to 5.0V the AVR output is when sourcing ~3mA).

\$\endgroup\$
1
  • 1
    \$\begingroup\$ I second this. Also, to avoid power sequencing issues, it would be MUCH better to avoid driving it with 5V IO. One option nobody mentioned yet is to configure your output as open-collector (or open-drain). Then you could drive it directly from your processor with no signal conditioning or glue logic. \$\endgroup\$
    – user57037
    Feb 7, 2017 at 23:50
0
\$\begingroup\$

The pull up resistor would be on the gate side of the CMOS gate. Whenever a single-throw switch (or any other sort of gate output incapable of both sourcing and sinking current) is being used to drive a CMOS input, a resistor connected to either Vdd or ground may be used to provide a stable logic level for the state in which the driving device’s output is floating.

Here is a picture showing what I am explaining here:

enter image description here

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.