I am referring to Xilinx FPGA P/N: XC6SLX45-2FGG484C (Spartan-6)

Link for part: http://www.digikey.com/product-detail/en/xilinx-inc/XC6SLX45-2FGG484C/122-1674-ND/2408284

Link for pinout: https://www.xilinx.com/support/packagefiles/s6packages/6slx45fgg484pkg.txt

My query is, if I want to use SPI interface for ADC,Touch and memory.. Do I need to use any GPIO's or dedicated SPI I/O's only ( SCK,MOSI,MISO,CS)?


1 Answer 1


As it is an FPGA, you can use whatever GPIOs you want for doing SPI. You are defining the SPI on a hardware level and can attach it wherever you would like (within reason).

FPGAs generally only have dedicated hardware for things like high speed serialization, microprocessor cores (see the Xilinx Zynq family or Altera Cyclone V), or memory interfaces (including dedicated memory blocks). Everything else is entirely defined by you (which is awesome).

The dedicated SPI pins are actually for configuration purposes. An SPI flash memory can be attached to those pins and the FPGA will read it when it starts up to load its configuration bitstream. The "Configuration" section in the Spartan-6 family manual talks about using SPI for initializing the device. There is usually a list of compatible SPI flash devices somewhere in the datasheets and reference manuals. The Spartan-6 is wildly popular, so I'm sure you will have no trouble finding information on those devices should you decide to use SPI for configuring your FPGA.

Short answer: You actually don't want to use those pins for your SPI interface. Those particular pins are meant for automatically configuring the device when it starts up.

  • \$\begingroup\$ Thanks Los for your answer. 1) Does it means, for SPI hardware config it requires more hardware block in spartan 6 ? 2) Same applicable to XC95288 (P/N : XC95288XL-10PQG208C ) which is Xilinx CPLD and has only GPIO's? \$\endgroup\$ Commented Feb 8, 2017 at 4:40
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    \$\begingroup\$ 1) The SPI bitstream loader is built in to the FPGA and does not require using any of the logic blocks. Your SPI interface to your ADC, touch, etc will require using logic blocks since it will be programmed by you in VHDL or Verilog. \$\endgroup\$ Commented Feb 8, 2017 at 4:42
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    \$\begingroup\$ 2) A CPLD stores its bitstream internally and does not require an external SPI flash. So, it doesn't have an interface for loading the bitstream from flash. For your SPI interface talking to your ADC, touch, etc you will need to use logic blocks. Side note: CPLDs generally don't have a lot of user logic blocks and you may not fit an SPI interface on there (or the SPI will take up all of the room, leaving nothing for your application logic). \$\endgroup\$ Commented Feb 8, 2017 at 4:43
  • \$\begingroup\$ Thanks .. and what about non volatile memory for Spartan 6 for storing results (say N numbers), even if we power off FPGA.. Is it there inbuilt ? I can see Total RAM Bits 2138112 in Spartan 6 , but not non volatile memory. \$\endgroup\$ Commented Feb 8, 2017 at 4:48
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    \$\begingroup\$ There is no non-volatile memory on an FPGA. You need to provide it separately and it can't be the same device as the flash used for configuring the FPGA. You could always get two SPI flash chips and hook one up to the dedicated SPI pins for your bitstream and another up to your application SPI interface with your ADC, etc and use that for storing data between power-ons. I'd also suggest looking at higher end microcontrollers instead as they are significantly cheaper than FPGAs, usually simpler to program, and may work for your application (unless your ADC is in the gigasample range of course). \$\endgroup\$ Commented Feb 8, 2017 at 4:52

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