My basic application involves sending ADC samples to PC via Ethernet. The ADC sampling and storing is happening in VHDL section while the Ethernet socket programming code is in Microblaze processor.

Microblaze is running at 60MHz and the FPGA is at 100MHz (I've taken care of the CDC issue). For transferring 1k data it takes me 740us. I have a dual port BRAM where the samples are stored and upon an interrupt Microblaze will read it from the second port. For simplicity I have kept the BRAM read in always enabled state and I am reading the data based on address only.

Any ideas as to how I can transfer the data in a faster way.

I've added the BRAM connection details for more reference. I've used the simple dual port type BRAM.

Buf_2k : Ethernet_test_data
    clka => ADC_clock,                      --10MHz clock
    wea(0) => BRAM_wr_en,                   --Write enable generated synchronously to ADC_clock
    addra => buf_wr_addr(10 downto 0),      --BRAM address generated similarly as write enable
    dina => ADC_data_trig,                  --Registered ADC data to be stored in BRAM
    clkb => CLK_50M,                        --50MHz clock generated from DCM
    addrb => BRAM_addr(10 downto 0),        --Address coming from Microblaze to read the data
    doutb => BRAM_dout                      --This data out is directly connected to Microblaze
  • \$\begingroup\$ 1k what? bits? bytes? packets? It'll come down to, how many clock cycles does it take for the CPU to read the BRAM. The CPU is dead slow compared to the FPGA side. \$\endgroup\$
    – user16324
    Feb 8, 2017 at 12:25
  • \$\begingroup\$ It's 1k bytes. So for reading one location it takes 740us/1024 (no of bytes) i.e. approximately 722ns. And I have only 2 statements for this process, one for providing address and one for latching the data. \$\endgroup\$
    – samjay
    Feb 9, 2017 at 3:36
  • \$\begingroup\$ Can you show how the BRAM connects to the Microblaze - it cannot connect directly to the processor, so what items in the subsystem do you have to connect it in (eg. LMB?) Also what version of Microblaze is this? \$\endgroup\$ Feb 15, 2017 at 14:48
  • \$\begingroup\$ Yes, the data and address lines (read port) of the BRAM are connected directly to the lmb of the processor, which then goes to a GPIO for further usage. I am using the 14.4 EDK version with Microblaze IP version 8.40b. \$\endgroup\$
    – samjay
    Mar 3, 2017 at 11:07

1 Answer 1


Any ideas as to how I can transfer the data in a faster way.

You could potentially use the FSL (or AXI-Stream in newer microblazes), as that is a single cycle "read from FIFO" into register.

But really the question is what do you mean by faster transfers?

The data is already "in the Microblaze subsystem" once it is in a BRAM that the MB can access. The processor can only go as fast as it can go, you cannot get the data any more tightly coupled than it already is (assuming the BRAM is directly connected to an LMB), the BRAM access is very quick. Have a look at the assembly code for the loop in which you are reading the data - there is probably a lot of stuff going on (all of which is necessary if you have the C-optimiser turned on).

You are measuring 42 cycles per 32 bit read, which sounds quite slow. Some thoughts:

  • Are you processing the data in the loop which reads it?
  • Is your loop code in cache, or are you running from some external memory?

In the best case of just reading the data to a register and then ignoring it, you could achieve a few cycles per word.

  • \$\begingroup\$ By faster I mean, faster than the 42 cycles it takes to do one 32 bit read. And yes this is in a loop to read 1k such locations. As for the BRAM, my current BRAM is in VHDL section, and also to transfer it's data to the BRAM connected to LMB will take similar time, right? Thanks for your suggestion for the AXI extreme transfers, I will look into that too. \$\endgroup\$
    – samjay
    Feb 14, 2017 at 6:17
  • \$\begingroup\$ Can you post a block diagram of the system, I may have misunderstood your wiring... the 2nd port of your VHDL BRAM should be wired straight to the LMB of the Microblaze for best performance. (Still 42 cycles sounds like a lot - is that for the whole loop or just the actual read, can you post the code of the loop?) \$\endgroup\$ Feb 14, 2017 at 9:46
  • \$\begingroup\$ I've edited the question by adding the BRAM connection details. This might help you in scrutinizing the issue. \$\endgroup\$
    – samjay
    Feb 15, 2017 at 6:04

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