I want to make a test bench for my mux21 but can't find a way, and online there is nothing clear, here is my code.

   library IEEE;
use ieee.std_logic_1164.all;

entity mux21 is
port( a,b,sel: in std_logic;
    s: out std_logic);
end mux21;

architecture arch_mux21 of mux21 is
with sel select s<=
    a when '0',
    b when '1',
    '0' when others;
end arch_mux21;
  • 1
    \$\begingroup\$ Searching this ssite for "VHDL testbench" produces a lot of useful answers. \$\endgroup\$ – Brian Drummond Feb 8 '17 at 23:27
  • \$\begingroup\$ so what you are looking for ? \$\endgroup\$ – tollin jose Feb 21 '17 at 8:17
library IEEE;
use ieee.std_logic_1164.all;

entity mux_21_TB is
end mux_21_TB;

architecture tb_arch of mux_21_TB is
    signal tb_a   : std_logic:= '0';
    signal tb_b   : std_logic:= '0';
    signal tb_sel : std_logic:= '0';

    signal tb_s   : std_logic:= '0';

    UUT : entity work.mux21
    port map (
        a   => tb_a,
        b   => tb_b,
        sel => tb_sel,

        s   => tb_s  

        tb_a   <= '1';
        tb_b   <= '0';
        tb_sel <= '1';

        wait for 10ns;
        tb_sel <= '0';

        wait for 20ns;
        tb_a   <= '0';
        tb_b   <= '1';

        wait for 10ns;
        tb_sel <= '1';

    end process;

end tb_arch;
  • \$\begingroup\$ This is testbench for your module. If you have any questuins feel free to ask. \$\endgroup\$ – Roman Feb 28 '17 at 3:38
  • \$\begingroup\$ Well, the problem i found out is in modelsim itself, as when i type begin after decalring the signals, the rest of the code is excluded from the architecture bloc. \$\endgroup\$ – Hani Harzallah Mar 2 '17 at 8:57
  • \$\begingroup\$ @HaniHarzallah what did you mean? how code can be excluded? Did you have any errors during compilation? \$\endgroup\$ – Roman Mar 3 '17 at 1:31
  • \$\begingroup\$ No error during compilation, but when i press simulate, i get "error loading design" \$\endgroup\$ – Hani Harzallah Mar 4 '17 at 8:43
  • \$\begingroup\$ @HaniHarzallah which simulator do you use? \$\endgroup\$ – Roman Mar 6 '17 at 6:17

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