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I have an accelerometer sensor which must be placed 1 m from my microcontroller. I can choose whether to place the ADC near the sensor or the controller.

I understand that longer distances from the sensor contribute more voltage fluctuation pre-ADC (noise). Longer distances from the microcontroller increase SPI errors and limit my transfer rate.

If I need to clock the SPI transfers to 4 MHz, where should I locate the ADC? Will the 1m distance be limiting my transfer rate? Will 1 m of pre-ADC wire contribute significant noise?

Notes:

  • The ADC has a 0 – 5 V input range, I care about steps in the 10 mV range (1/500th of the range). If my noise peaks are below that the application will be successful.
  • The wires between the ADC and sensor will carry 3 Vout channels, ground, and 5 V.
  • The sensor, wires, and (depending on placement) the ADC will undergo impacts as the application is impact characterization. Impacts will be due to dropping with an estimated peak g force of 150 g for 2 ms.

Accelerometer specs

enter image description here

Update: I decided to run the ADC close to the pi (~6 inches) and the sensor far from the pi (~0.75m) as the analog noise sounded easier to troubleshoot than the digital errors. I currently get a baseline of ~61mV from the sensor with a standard deviation of 10mV (based on ADC readings). Peak to trough noise levels are about 60mV. This is a decent start but I think I have some improvements to make in the circuit design. For example, without a sensor attached I get a fluctuation of about 100mV on the scale of 1Hz. I'm going to improve my Vref and grounding scheme and see if I can remove some of this noise. Thus far I don't think my main issue is cabling, though insight is welcome. Also found this useful reference: http://ww1.microchip.com/downloads/en/AppNotes/00688b.pdf

Update:

My final circuit was drastically improved from the first so it will be hard to say exactly what changes were responsible for the improvements. My initial design didn't include decoupling capacitors, a dedicated reference voltage, and also had multiple paths to ground. I eventually designed and got a PCB fabricated for about 20 bucks + shipping. With this system, a 0.75m length of 10 wire IDC cable carrying the analog voltage to the ADC, and IDC connectors here is my result:

enter image description here

The right axis shows the integer output of the ADC. The standard deviation of that variance in y is about 3 units (mV) and in z is about 4.1 units. Peak to trough is about 20 units. This is a huge improvement over the first design and I'm very happy. decoupling capacitors and a reference voltage were critical it seems. Going throught the whole process of getting a board fabricated was super fun as well.

I can't explain the increased variance for the z channel. It is furthest from my power/ground wires. It is the last wire on the end of the flat cable, so that could be it.

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  • \$\begingroup\$ Do you have to pass emissions testing? Or is this hobbyist in nature? What does "undergo impacts" entail? \$\endgroup\$
    – M D
    Feb 9, 2017 at 5:29
  • \$\begingroup\$ Ah, the sensor will be dropped and I expect a peak g force of 150g for 2ms. If the ADC is placed near the sensor it will feel the same forces. \$\endgroup\$
    – nate
    Feb 9, 2017 at 5:37
  • \$\begingroup\$ 150 g ?! That sounds like a bit much for sensitive electronics. \$\endgroup\$
    – Marcus Müller
    Feb 9, 2017 at 8:28
  • \$\begingroup\$ I mean, yes, electronics can withstand that, but usually by being enclosed in something that absorbs quite a lot of the resulting forces \$\endgroup\$
    – Marcus Müller
    Feb 9, 2017 at 8:34
  • \$\begingroup\$ It's a 3mm amplitude of 250Hz vibration. Crazy stuff :) \$\endgroup\$
    – user76844
    Feb 9, 2017 at 8:37

2 Answers 2

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Longer cable distances do not imply noise unless:

  1. The cable is picking up RFI (shielded cables help mitigate this)
  2. There is additional crosstalk from mutual inductance between the conductors of the cable. (really depends on the cable, conductor size and distance and wiring scheme)
  3. Your return current from both analog and signal ground has a common ground and creates common mode noise (a ground plane has low resistance compared to a cable)

I personally would just start building cables, do a short one and test the noise. Then test with a long one, if the noise is more than you need to start looking into the described effects and redesign the cable. It might also be advantageous to put the voltage reference and LDO with the ADC on the end of the cable.

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  • \$\begingroup\$ I'll build some cables this weekend. There are some additional practical constraints on the flexibility of the cable, so I'll have to see what kind of fluctuation I end up getting. \$\endgroup\$
    – nate
    Feb 9, 2017 at 19:49
  • \$\begingroup\$ Could you clarify one thing - the suggestion of an LDO brings up a good point. In either placement of my ADC, the reference or signal voltage will be traveling 1m and thus be susceptible to noise. Is it correct that the noise due to the reference voltage fluctuations will be smaller than that of the signal because the average voltage is higher? \$\endgroup\$
    – nate
    Feb 9, 2017 at 19:51
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    \$\begingroup\$ The LDO and reference guarantee that the voltage between the ground and output is constant. If you put it down the cable the source impedance is increased, and the analog voltage and reference are more susceptible to noise. I also suspect that common mode ground noise would be decreased, but I have not tested that theory yet. I know from a noise standpoint alone you'll have a better result and potentially one less cable to run for the reference. I'm not sure what the question is about reference noise, but references do have noise and it contributes to your ADC error budget. \$\endgroup\$
    – Voltage Spike ♦
    Feb 9, 2017 at 21:05
  • \$\begingroup\$ What reference noise contributes relative to the signal I can't say, because you have to know what the signal noise is. \$\endgroup\$
    – Voltage Spike ♦
    Feb 9, 2017 at 21:05
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Generally it's better to put ADC as close as possible to the analog source (thanks, Jonas). Digital signals a piori are more noise immune than analog ones. Just as example: capacity between 1m cable and power grid is enough to inject common mode of couple of tens milivolts, sometimes 300mV. Are you sure your CMRR will be good enough? You never know.

So put ADC as close as possible. But SPI over 1m (cable or PCB) is not trivial, you should take care on that. First, use differential signals- you don't want common mode interference. Then note that differential transmitters and receivers have delays. SOmetimes the delay is significant enough to shift the received data against the clock. So if you sample the ADC with FPGA it's not a problem, but in CPU you have to find the correct mode.

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  • \$\begingroup\$ Point is that OP says he needs 9 bit resolution (500 steps); let's assume that implies a 10 bit ADC. Then we know that he's got an SPI clock of 4 MHz – implying a max sample rate of 400 kHz, implying a max signal bandwidth of 200 kHz. 200 kHz sounds pretty feasible for properly shielded microphone cable over 1m, tbh, at studio sound qualities (audio people are strange – they use 24 bit ADCs), especially if the accelerometer actually modulates current, not voltage. \$\endgroup\$
    – Marcus Müller
    Feb 9, 2017 at 8:46
  • \$\begingroup\$ as close as possible to the analog source. I feel this could be clearer in the answer. \$\endgroup\$
    – Jonas Schäfer
    Feb 9, 2017 at 8:48
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    \$\begingroup\$ @GregoryKornblum point is that we probably agree on "best here is to put the ADC close to the signal source, then build a robust digital transceiver"; I'm not convinced ensuring a 4 MHz wide digital signal is undamaged is that much easier than using good cabling with an accelerometer that was probably designed for being used with 1m of cable – the ones I know actually came with a small coax connector, over which is was bias-supplied and on which it modulated the signal without any measurable loss. \$\endgroup\$
    – Marcus Müller
    Feb 9, 2017 at 9:10
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    \$\begingroup\$ @MarcusMüller, rephrasing what you are saying: one can screw up both analog and digital signals. Yes, this is right. Still, for digital communication there is a ready infrastructure: CAT5 cables, RJ45 connectors, transceivers, ESD protection, isolation. Analog would require some video grade cables which also exist, but are less common, i think. \$\endgroup\$
    – user76844
    Feb 9, 2017 at 9:16
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    \$\begingroup\$ Let's hope he will tell us what he decided and what came out :) \$\endgroup\$
    – user76844
    Feb 9, 2017 at 9:22

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