The InvenSense MPU-9250 datasheet specifies not only a maximum VDD rise time (100 ms), but also a minimum rise time (0.1 ms). It seems like the more common concern in power supplies is reducing the rise time. Why wouldn't a faster rise time be better? What kinds of problems would the minimum limit be trying to prevent?
During Power On Reset, there is a special analog circuit that detects the VDD change and decides to reset the processor. If the change on VDD is not fast enough, the POR circuit could decide that it is not a real power up event and leave the processor unresetted. Starting a digital machine with no reset is prone to all kinds of failures since the internal registers and volatile memories start with garbage contents. And as it is well known, garbage-in produces garbage out.
With millions transistors, each transistor has capacitance, so it takes some time for each of the gates to its VCC to a voltage level for designed behavior. There is also a small amount of inductance from the wires and that will contribute to the rise time. Another problem is metastablity
The second thing is the clock. Once all the transistors Vcc lines reach an appropriate level and the clock is running the reset network can be switched off. The reset network is built to allow registers (and memory) to come up in a ground state. Any state machines are also in their ground state. This is important because we want a clean slate when we start the processor when code is being ran.
If you don't reset for an adequate amount of time, the processors memory could be left with old information or random information. The other problem is meta stability with the system being 'in between' logic levels.
It does seem a little long for an IC, Usually digital logic only takes a few clock cycles to clear out the registers, In the case of the MPU-920 there is also analog circuity which could have something to do with it. Maybe the engineers set the time arbitrarily long just to be safe.