The InvenSense MPU-9250 datasheet specifies not only a maximum VDD rise time (100 ms), but also a minimum rise time (0.1 ms). It seems like the more common concern in power supplies is reducing the rise time. Why wouldn't a faster rise time be better? What kinds of problems would the minimum limit be trying to prevent?

  • 1
    \$\begingroup\$ The answers below describe what can happen when the supply rises too fast or too slow. In addition to that there is the fact that the manufacturer cannot check that the IC starts up properly for every rise time. They only test (and thus guarantee) only the specified range. So they decided that 0.1 - 100 ms is a practical range, test with that and guarantee that the chip works for that. It is not said that anything outside this range does not work, it can work, but there is no guarantee. \$\endgroup\$ Feb 9, 2017 at 6:57

2 Answers 2


During Power On Reset, there is a special analog circuit that detects the VDD change and decides to reset the processor. If the change on VDD is not fast enough, the POR circuit could decide that it is not a real power up event and leave the processor unresetted. Starting a digital machine with no reset is prone to all kinds of failures since the internal registers and volatile memories start with garbage contents. And as it is well known, garbage-in produces garbage out.


With millions transistors, each transistor has capacitance, so it takes some time for each of the gates to its VCC to a voltage level for designed behavior. There is also a small amount of inductance from the wires and that will contribute to the rise time. Another problem is metastablity

The second thing is the clock. Once all the transistors Vcc lines reach an appropriate level and the clock is running the reset network can be switched off. The reset network is built to allow registers (and memory) to come up in a ground state. Any state machines are also in their ground state. This is important because we want a clean slate when we start the processor when code is being ran.

If you don't reset for an adequate amount of time, the processors memory could be left with old information or random information. The other problem is meta stability with the system being 'in between' logic levels.

It does seem a little long for an IC, Usually digital logic only takes a few clock cycles to clear out the registers, In the case of the MPU-920 there is also analog circuity which could have something to do with it. Maybe the engineers set the time arbitrarily long just to be safe.

  • \$\begingroup\$ usually the reset time is not influenced by the time needed to clear registers which is indeed small, but mainly by the time needed for the internal PLLs to settle. \$\endgroup\$ Feb 9, 2017 at 7:09
  • \$\begingroup\$ It depends if you are using dual rank synchronizer to sanitize your inputs you'll need at least two clock cycles to clear the registers. \$\endgroup\$
    – Voltage Spike
    Feb 9, 2017 at 16:29

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.