How is it possible that the reverse transfer capacitance of this FET is so low?

Question

A FET has parasitic capacitance, which can be modeled as a capacitor between each of its terminals (gate, drain and source), which I refer to as C_gd, C_gs and C_ds, as shown in the image below.

FET manufacturers list other capacitances in their datasheets, which are refered to as input capacitance C_iss, output capacitance C_oss and reverse transfer (or Miller) capacitance C_rss. As far as I know, these capacitances are measured as follows:

• C_iss is measured by shorting drain and source, so it really is the parallel capacitances C_gd and C_gs, hence: C_iss = C_gd + C_gs

• C_oss is measured by shorting gate and source, thus it is C_oss = C_gd + C_ds

• C_rss is measured between gate and drain (without shorting anything), therefore it is C_gd plus the series capacitance of C_gs and C_ds: C_rss = C_gd + 1 / (1/C_gs + 1/C_ds)

However, when I take a look at the datasheet of an AO3162, there is something strange: this device has typical values of C_iss = 4.2 pF, C_oss = 0.45 pF and C_rss = 0.05 pF.

C_gd must be very small, so I approximate C_gs = C_iss and C_ds = C_oss. However, the series capacitance of these is 0.41 pF, much larger than the measured value for C_rss. How is this possible?

Answer 1

\$C_{rss}\$ is not measured by putting a capacitance meter between gate and drain, and leaving the source open.

It is inferred from the ramping behaviour, which is largely controlled by the Miller capacitance, the gate current needed to charge up the \$C_{rss}\$ capacitor, when the drain is slewing in voltage.

This is equivalent to making a three-terminal capacitance measurement across gate and drain, with a guard terminal on the source. This is capable of measuring all three capacitors in that diagram independently, even for the very different values that are shown.

Answer 2

Part of the answer can be inferred from Rds(on) which is 500 ohms (max), ten thousand times the Rds(on) of a typical switching MOSFET (say, 0.05 ohms).

High power switching MOSFETs are generally implemented as thousands of smaller MOSFETs connected in parallel, which makes them amenable to VLSI manufacturing processes, but tweaked for higher voltage.

The individual ON resistances of each FET sum in parallel to make the absurdly small values (milliohms) you see for the whole device.

Unfortunately the parasitic capacitance values also sum in parallel, which is why the pF values you'd expect for an individual MOSFET grow to the nF values you see for the total device.

So. if we also scale the Crss by 10000, we would see 500pf(typ) or 700pf(max) which is closer to the values you'd expect for a scaled 50mohm device.

Hence my hypothesis is that this device is a single FET or a small array (2,4 or so) optimised for low current switching where a few hundred ohms Rds(on) don't matter. Die photos would be interesting...

However it's not a full explanation, as the (scaled by 10000) Crss isn't quite in the typical nF range.

But notice the breakdown voltage is unusually high, at 700V? That implies unusually thick dielectric layers, to keep the field strength (in volts/metre) between drain and everything else down to normal limits.

And increasing the dielectric thickness in any capacitor will reduce capacitance.

Between these effects (scaling, and tuning for high voltage) I think we can explain the unusually low capacitance.