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I am studying for an exam about memory (mostly cache) and I ran across a multiple-choice question from a few years back:

Which cache type is recommended for bus watching and is also used in multiprocessor systems?

 a. write-through cache
 b. write-back cache

I understand that bus watching means that each cache snoops the bus to see what requests are sent form other caches to the main memory, but I don't really understand which answer is correct.

First type (write-through) would just update everything to the memory every time something is updated and the latter would just keep data in cache to be faster and to me it seems that both could work.

Any help is appreciated.

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    \$\begingroup\$ The question is ambiguous. Both types are used in multiprocessor architectures, they can be combined (for example write-thru L1, write-back L2, shared multi-cpu write-back L3...). If bus watching is for debugging, a write-thru cache is obviously more adequate. \$\endgroup\$ – TEMLIB Apr 23 '17 at 20:15
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Obviously on a multiprocessor system a write-back cache is impossible to use. The write-back cache only updates the data in the cache and not in the memory. The update on the memory is done only when the data on the cache is to be evicted. Let's say that two processors have the same memory address mirrored on their respective caches. Each one of them decides to change the cache contents. Here starts the problem, there are two different data for the same memory addresses. Hence it is impossible to use write-back caches for multi-processor system unless additional mechanisms are added to ensure cache coherency between the different processors of the multiprocessor system.

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    \$\begingroup\$ Actually, cache coherency protocols for write-back caches in multiprocessor systems are quite common. And even without them, the operating system software can be careful about how memory is shared between threads running on different CPUs in the first place. "Impossible" is too strong a word here. \$\endgroup\$ – Dave Tweed Feb 22 '17 at 12:28
  • \$\begingroup\$ Even for write-thru caches, there must be some coherency protocol/bus snooping to force cache invalidation when a "write with kill" transfer occurs. Traditional "MEI" vs. "MESI"... \$\endgroup\$ – TEMLIB Apr 23 '17 at 20:09
  • \$\begingroup\$ @TEMLIB: In a multi-processor system that uses write-through caching, bus snooping can be accommodated with essentially the same bus connections that a processor would use to write the bus itself, without any requirement that any bus master know whether any other masters have caches. \$\endgroup\$ – supercat Apr 9 '18 at 20:48
  • \$\begingroup\$ @supercat: Yes, bus snooping with WT caches don't need extra signals, even for symmetric multiprocessing. \$\endgroup\$ – TEMLIB Apr 9 '18 at 22:07
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This question seems a little dated since most multiprocessor CPUs don't really have a "bus" anymore.

Write-back(WB) is the standard caching methodology for multiprocessor architectures today. Write-through(WT) basically doubles the transactions by sending everything to memory and to cache at the same time. For visibility/debug, you'd want to see every transaction in as many places at once. So if we're calling the path to memory the "bus", then WT would allow you to see every transaction happening to the caches out at memory. I would suspect this is probably the answer they're looking for. Although WT can be used in a multiprocessor cpu it's generally only used for very small address ranges for specific things. The rest of the cache on modern multiprocessor cpus uses WB instead because of its performance benefits.

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