I'm finding difficulty in understanding how the propagtion delay of this full adder is calculated in this primitve manner. Please see the following attached:

1) Lecture slide explaining worst case delay 2) Past Exam Question to calculate delay 3) Past Solution to exam question

For exam question (d, part i), I am still unsure how the answer is still 3 gate delays. I know S3:0 has changed from 0101(5) to 0110(6), more particularly bit S0 has changed from 1 -> 0 and bit S1 has changed from 0 -> 1. Bits S3 and S2 have remained the same.

Could you please walk me through which path was taken to calculate it's worst case delay (i.e 3 gate delays in this case)?

Many Thanks

  • \$\begingroup\$ You just count the number of gates that the signal must pass through before it arrives at the output (from the input). Don't confuse gate delays with # of transitions. \$\endgroup\$
    – jbord39
    Feb 10, 2017 at 0:15
  • \$\begingroup\$ May I ask what the signal is that you are referring to? Is it S0 or S1 or both? \$\endgroup\$
    – Arsenal123
    Feb 10, 2017 at 0:25

1 Answer 1


Initially your carry outs are as follows

\$C_0 =0\$
\$C_1 =0\$
\$C_2 =0\$

\$P @ t=0\$ is '001'
At t=1 it becomes '010' as in

\$Q=4 => '100'\$ so if we were to look at the additions at the carry outs they do not change.

Since you are adding You are going from
\$P_0+Q_0=0+0=0 \rightarrow C_0=0\$ (No carry change )
\$P_1+Q_1=1+0=1 \rightarrow C_1=0\$ (No carry change)
\$P_2+Q_2= 0+1=1 \rightarrow C_2=0\$ (No carry change)

Since there are no carries the result of each adder goes to straight to the sum and there are no interactions between the adders since all your carries unchanged throughout the transition.

It takes 3 gate delays to get from Input of a value(Q or P) into the adder to the output(S or C) of it hence the answer is 3 gates.

  • \$\begingroup\$ Did you just went to sleep? May I please ask you to complete the answer? \$\endgroup\$
    – User323693
    Feb 10, 2017 at 0:35
  • \$\begingroup\$ Sorry went on to edit \$\endgroup\$
    – zoder
    Feb 10, 2017 at 0:36
  • \$\begingroup\$ Apologies, was getting late. Just saw the answer, many thanks @ Zoder \$\endgroup\$
    – Arsenal123
    Feb 10, 2017 at 9:33
  • \$\begingroup\$ Yeah for these things you have to break em down in real small pieces ;) best of luck \$\endgroup\$
    – zoder
    Feb 11, 2017 at 3:16
  • \$\begingroup\$ @Zoder, Hi. I'm still finding difficulty in working out the longest delays paths for part ii) and iii) of the question. For instance in part ii): @t=0, initially the carrys are, C0=0, C1=0, C2=0 @t=1 P0+Q0=1 => C0=0 P1+Q1=1 => C1=0 P2+Q2=1 => C2=0 Hence should'nt the answer be 3 gate delays as there is no change in the carries? Also is "3 gate delays" in reference to the full adder, i.e 1 delay per 1-bit adder? \$\endgroup\$
    – Arsenal123
    Feb 11, 2017 at 18:37

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