Dissipating Heat from Tiny Components

Question

I need a 5v 2.5A output in a handheld device and have settled on the TPS61235P. Its 2.5mm QFN package was very hard to solder, but I finally got a board fabbed and tested it out. After roughly a few minutes of constant on-time @ 2.5A, the input traces started to burn up.

Now for the next PCB I'm planning on using the wider traces with solder mask left off so I can tin the entire trace up to the chip.

But once I solve this, I'm left wondering, how do I keep the chip cool? It seems way too small for a heatsink, and doesn't have a solder pad similar to other chips I've used.

I assume a schematic won't be necessary, but I am attaching a pic of the current prototype pcb.

Answer 1

You want to have the the pads connected to large areas of copper in this case to dissipate the heat. I suggest you review section 11 on layout and thermal considerations when laying it out, and follow the recommendations as much as possible. Notice how large the copper areas are, and how many vias are used. These both help dissipate heat from the IC.

@1N4007 is right about the thermal calculations, but keep in mind the 28ºC/W figure is usually based on a certain amount of copper area. I wasn't able to find that specified in the datasheet, but often it's 1 sq.in of copper, so you may not get 28ºC/W from the chip alone, i.e. in free air.

Answer 2

Although I'm a little surprised as you at the lack of a pad, a quick back-of-the-napkin calculation makes me think you may be OK as-is.

The datasheet shows you stay above 90% efficiency through the entire operating range. And with [email protected], you're dealing with 12.5W...so you may dissipate, at worst, 1.25W. Multiply that by your 28C/W Junction to Ambient, and you come up with 35 degrees C. Subtract from your 125C maximum junction temperature, and you get 90C ambient. So as long as the air around the chip is less than 90C, you should be OK.

By the way, if you can afford the cost, you might be able to save yourself the trouble of manually tinning the traces by increasing the thickness of the copper on your outer layers. I can't tell at a glance what the copper thickness of that board is, but if you specify "2 ounce" copper for outer layers, it will result in thicker traces and a larger cross section to carry current. Default is usually 1/2 oz or 1 oz.

Answer 3

Vias with 1:1 ratio of circumference to height thus contain a SQUARE of Copper; the thickness may be 20 microns or 35 microns or otherwise, depending on how long the board house ran the via-plating step.

One square of 35 micron copper is 70 degrees Cent per watt.

Thus each via is 70 degrees Cent per watt.

And heat attempting to spread out lateral, on the surface, is also limited by that 70 degree Cent per watt per square.

Suppose the heat is generated in a corner of the PCB. What is the thermal resistance to rest of PCB?

What if heat is generated in MIDDLE of a PCB?

^{simulate this circuit – Schematic created using CircuitLab}

Answer 4

Consider heat, entering a single square of foil. Perhaps from the 2mm tab of SOT-23, or 1cm^2 tab of TO-220. What is the thermal resistance to the surrounding PCB. Surround that single square, of whatever size, with a 3*3 grid, the heat injected into the middle square. There are 8 squares around the center; the thermal resistance out of that center square is $$(70degree C/watt) / 8$$ or 9 degree C/watt. Now consider a 5*5 grid. What additional thermal resistance does the outer ring 4+4+4+4 squares contribute? Just divide $$(70degree C/watt)/12$$ or 6 degree C/watt. If the original IC (heat source) has Rthermal of 25 degree C junction_to_case, then we just add 25 + 9 + 6 = 40 degree C/watt.

^{simulate this circuit – Schematic created using CircuitLab}

What if these 5*5 squares need to dump heat into the underlying GND plane? The Rthermal of epoxy-fiber glass is about 200X that of Copper foil. You can use the Rthermal of copper cubes, 1/(340 watts/degree C * meter) or 1/(3.4 watts/degree C * cm) and scale down further for 20 mils or 60 mils thickness. Then scale up by 200X, as approximation for FR-4.

Get a quadrille pad, and start sketching heat flows through grids, laterally, and vertically through vias and FR-4. Or generate 2_D grid of resistors in SPICE, with foil on the surface using low values, and FR_4 between layers using 200X higher Rvalues (in both x & y, to make a cube of FR-4).

Answer 5

To beter dump heat into the underlying plane, have the stackup use the minimum allowed thickness between layer1 and the GND plane (large GND region) on layer2. And remember the large heat-dump pads that TI suggests:

To dump heat even better, enlarge that SW region under the IC. The TI appnote ignores the 70degree Cent per watt per square of foil. There are 3 or 4 squares from middle of the "SW" pad to the "SW" region where the inductor is soldered. Yet the SW pad is the DRAIN of the internal FET switch, the main heat generator.

^{simulate this circuit – Schematic created using CircuitLab}