# Verilog Error: System task finish is always executed

I'm using a Mimas V2 with a Spartan 6 CSG324 LX9. Trying to teach myself to use Verilog and I've been using this tutorial. I've had no issues running VHDL modules and running just this code Verilog code (which appears towards of the problematic chunk further down) seems to work:

module myModule(A, B);
input wire A;
output wire B;
assign B = !A;
endmodule


Doesn't really do much though, as the inputs and outputs aren't set up to do anything though.

It seems to be having a problem with line 15 here:

module myModule_tb();
wire out;
reg clock;

always begin
#1 clock =!clock;
end

initial begin
//Initialize clock
clock = 0;

//End simulation
#10
$finish; //<-------this line here end myModule notGate(clock, out); endmodule module myModule(A, B); input wire A; output wire B; assign B = !A; endmodule  The error message I get when I try to implement is HDLCompiler:1689 - "C:\Xilinx\Projects\Test2\myModule_sim.v" Line 15: System task finish is always executed. Now as best as I could tell, I followed all the steps correctly. I even went so far as to download the example files provided (the Mimas version) at the bottom of that tutorial, and it does the same thing. I understand roughly what the$finish task does, but I'm not sure why it's causing a problem here. Seems like it's fussing at me for expecting finish to do what it's supposed to do here.

I've tried a semi colon after the #10 on the preceeding line, putting them on the same line, commenting out #10, commenting out both #10 and $finish and I always get the same or an error related to not having$finish

Help! I'm not sure why ISE is rejecting that line!

• Are you simulating or compiling hardware? They are both two very different things. I don't know about verilog, but this looks like your trying to put simulation code on an FPGA. – Voltage Spike Feb 11 '17 at 7:37
• The tutorial specifically mentions clicking the "simulation" radio button above the hierarchy window (step 8), which I did. If I take out the module myModule_tb, I get an error saying the simulator is missing. I've tried running the Simulation Library Compilation Wizard, but it's asking me to point it to where the simulator executable is. I don't know where to get that. I spent about an hour trying to find ModelSim downloads on the Xilinx site but I either get pointed in circles or to dead pages. I'm guessing the problem is at least in part related to not having a simulator. Where to download? – Liz P Feb 11 '17 at 23:01
• Apparently ModelSim is actual made by a third party. I will report back once I have installed it now that I've found it! – Liz P Feb 11 '17 at 23:11

So I installed ModelSim and that somehow convinced ISE to stop complaining about \$finish. The weird thing is that I'm still not using a ModelSim simulator, it's using ISim. So I don't know what was wrong, but it works now :/ not totally helpful to future folks, sorry!