I'm using a Mimas V2 with a Spartan 6 CSG324 LX9. Trying to teach myself to use Verilog and I've been using this tutorial. I've had no issues running VHDL modules and running just this code Verilog code (which appears towards of the problematic chunk further down) seems to work:
module myModule(A, B); input wire A; output wire B; assign B = !A; endmodule
Doesn't really do much though, as the inputs and outputs aren't set up to do anything though.
It seems to be having a problem with line 15 here:
module myModule_tb(); wire out; reg clock; always begin #1 clock =!clock; end initial begin //Initialize clock clock = 0; //End simulation #10 $finish; //<-------this line here end myModule notGate(clock, out); endmodule module myModule(A, B); input wire A; output wire B; assign B = !A; endmodule
The error message I get when I try to implement is
HDLCompiler:1689 - "C:\Xilinx\Projects\Test2\myModule_sim.v" Line 15: System task finish is always executed.
Now as best as I could tell, I followed all the steps correctly. I even went so far as to download the example files provided (the Mimas version) at the bottom of that tutorial, and it does the same thing. I understand roughly what the $finish task does, but I'm not sure why it's causing a problem here. Seems like it's fussing at me for expecting finish to do what it's supposed to do here.
I've tried a semi colon after the #10 on the preceeding line, putting them on the same line, commenting out #10, commenting out both #10 and $finish and I always get the same or an error related to not having $finish
Help! I'm not sure why ISE is rejecting that line!