# Emitter follower biasing with voltage divider

I have met a emitter follower design example in the Horowitz-Hill's book (scheme is below):

And I don't understand why the resulting steps is correct:

Step 1. Choose $V_E$. For the largest possible symmetrical swing without clipping, $V_E = 0.5V_{CC}$, or $+7.5$ volts.

Step 2. Choose $R_E$. For a quiescent current of $1 mA$, $R_E = 7.5k$.

Step 3. Choose $R_1$ and $R_2$. $V_B$ is $V_E+0.6V$, or $8.1V$. This determines the ratio of $R_1$ to $R_2$ as $1:1.17$. The preceding loading criterion requires that the parallel resistance of $R_1$ and $R_2$ be about $75k$ or less (one-tenth of $7.5k×\beta$ ). Suitable standard values are $R_1 = 130k$, $R_2 = 150k$.

So, once again all known values: $$V_{BE} = 0.6 V \\ R_1 = 130K \\ R_2 = 150K \\ R_E = 7.5K \\ \beta = 100$$

My question is about values for $R_1$ and $R_2$. The maximum current through the divider without connected load is: $$I_{div} = \frac{V_cc}{R_1 + R_2} = \frac{15}{280 \cdot 10^3} \approx 54 \mu A$$

When we connect emitter follower to the divider, there must be a base current $I_B$ that is: $$I_B = \frac{I_E}{\beta + 1} = \frac{1ma}{100 + 1} \approx 9.9 \mu A$$

Hence we could calculate output voltage of the divider after connection of emitter follower: $$I_{R_2} = I_{div} - I_{B} = 54 - 9.9 = 44.1 \mu A$$

Hence, we'd get a output voltage from the divider: $$V_{div} = V_{R_2} = I_{R_2} \cdot R_2 = 44.1 \cdot 10^{-6} \cdot 150 \cdot 10^3 \approx 6.62 V$$

So, we would get a $6 V$ output from the emitter follower instead of expected $7.5 V$.

Could you tell me where I'm mistaken?

P.S.: There is also a screenshot from simulator:

• Step 4 - if you are dissatisfied with the output not being 7.5 volts, adjust one of the bias resistors. – Andy aka Feb 12 '17 at 11:01
• Thank you. It's the obvious step. =) But am I right with my statements? – vpetrigo Feb 12 '17 at 11:03
• Yes you are indeed. – Andy aka Feb 12 '17 at 11:06
• I don't understand why they point out that we should meet the condition $R_source = R_1 || R_2 \ll (\beta + 1) R_E$, but do not mentioned that it also should be $I_{B} \ll I_{div}$ – vpetrigo Feb 12 '17 at 11:11
• I think it's about input impedance/resistance (ie not to decrease it by choosing smaller bias resistors). – Rohat Kılıç Feb 12 '17 at 11:30

The book's approach is an estimation, on the assumption that the base current is negligible - which turns out to be not so great of an assumption here, as you found out.

your approach is more precise, but made the same mistake right here:

The maximum current through the divider without connected load is: Idiv=VccR1+R2=15280⋅103≈54μA

you didn't factor in the equivalent resistance on the base side: at 8.1v @ 10ua, that's equivalent to a 810K resistor (approximately Re * beta - see note below).

So the lower resistor R2 is paralleled by a 810K resistor. Once you factor that in your calculation, it will be alright.

Most people don't take that approach. for example, I typically set the current through R1/R2 to be 10x of the base current. That yielded R1 + R2 = 15v / 100ua = 150K. and go from there for R1/R2 individually. the 10x is picked to make sure that the base current is indeed negligible.

what it shows you is that 1) don't put too much stock in any book; and 2) don't take estimation too seriously. many times, good enough is indeed good enough.

edit:

note: for better approximation, some people would assume that the lower resistor is by-passed by a equivalent resistance of beta * Re -> 750K in this case, vs. 810K the real one calculated earlier. This approach works fairly well as an approximation.

• Thank you for pointing me out! I've forgotten to take into account the load impedance of emitter follower. – vpetrigo Feb 12 '17 at 18:48

Quote dannyf: "the 10x is picked to make sure that the base current is indeed negligibe."

Yes - of course, correct. However, for a better understanding I like to give some additional explanation.

The background of the commonly applied design criterion (divider current >> base current) is the fact that the ratio Ic/Ib=beta has very large tolerances. That means: For a selected collector current Ic we do not know the actual base current. Hence, we select a design in which the base current (and its large tolerances) play a minor role only.

As a consequence, we have a "relatively" low-resistive voltage divider (if compared with the input resistance at the base node) providing a "stiff" voltage at the base (as "stiff" as reasonable) - nearly independent on beta uncertainties.

(By the way: This works because the collector current is detrmined by the base-emitter voltage and not by the current Ib).