In this document, On semiconductor describe how to design a divide by 3 system using a Karnaugh Map:

Specify, Divide By 3,
50% duty cycle on the output
Synchronous clocking
50% duty cycle clock in
Using D type Flop flips and karnaugh maps we find;
Ad = A*B* and Bd = A
(Note: * indicates BAR function)

From this, they show this schematic:

From Karnaugh Map

Afterward, they say:

Using the technique, we add a gate on the clock to get differential Clock and Clock bar, a flip flop that triggers on the Clock Bar rising edge (Clock Neg.) to shift the output of ”B” by 90 degrees and a gate to AND/OR two FF output to produce the 50% output. We get Figure 2, a Divide By 3 that clocks synchronously with 50% output duty cycle.

And they show this schematic:

Divide by 3

I was hoping you could show me how they got to this schematic from the Karnaugh Map. I know it's used to simplfy boolean expressions but I didn't know you could design systems with this method.

I'm asking because I have no idea how to even approach such a question, let alone how to solve it. If anyone has a better idea than using a Karnaugh Map, I would love to hear it.

Thank you!

  • \$\begingroup\$ Is this homework? \$\endgroup\$ – skvery Feb 12 '17 at 17:01
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    \$\begingroup\$ A key to understanding this is to realise that the output needs to have one edge clocked on a rising edge referred to the input and the other edge clocked on a falling edge referred to the input. \$\endgroup\$ – Peter Smith Feb 12 '17 at 17:08
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    \$\begingroup\$ It's not homework, I have a job interview and I want to know how to solve this question. \$\endgroup\$ – nettek Feb 12 '17 at 17:26


A mod-3 counter with output high for only one state will work as a divide-by-3 system. But duty-cycle will be 1/3. The state table for which can be written as:

PresentState  Output  Nextstate
    0 0         0       0 1     
    0 1         0       1 0      
    1 0         1       0 0

This system needs two flip flops for implementation. We need to find out what should be connected to the inputs (D) of these flip flops. This is where K-map is needed. We have the table. Just translate to k-map and solve for Ad and Bd. (You actually don't need a K-map to solve for a 2-variable logic)


To make the duty-cycle 50%, the output should be high for 1.5 clock cycles instead of 1. If we can make a circuit that can shift the input signal by half a clock period (as BQ and CQ in 2nd figure), then ORing the input and output of such a circuit can give the required 50% duty-cycle.


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