I got questions about the working mechanism and measurement method of SPI and I2C interface. For SPI, there are several modes. My question is, how will the data be latched? Take CPOL=1 and CPHA=0 for example, the bit is latched at the falling edge of clock. But, why is it the same for MISO and MOSI? I mean, MISO and MOSI come from different devices(the former from device and the later from master). But the clock always come from master. So how would it possible to latch both MOSI and MISO by the falling edge of clock? For MOSI maybe yes, since the clock and the MOSI output together from master, and arrive device at the same time (maybe I should say half clock later). So it's possible for MOSI to follow the timing diagram. But for MISO, how do we let the MISO be latched at the center of its bit, since it'll travel an uncertain flight time from device to master? And for scope measurement, which point should we probe? MOSI on device side and MISO on master side?
I got the same question on I2C. How to make sure the SDA data will be kept high when it's from master to slave, and from slave to master, since the clock is always from master to slave?