6
\$\begingroup\$

I am trying to simulate a LDO with Microchip MCP6001 operational amplifier in LtSpice. With other OA simulation is ok, but with all Microchip models, the same error:

Time step too small; Initial timepoint: trouble with u2:nmi-instance m:u2:12

Here is the model with trouble

.SUBCKT MCP6001 1 2 3 4 5
*               | | | | |
*               | | | | Output
*               | | | Negative Supply
*               | | Positive Supply
*               | Inverting Input
*               Non-inverting Input
*
********************************************************************************
* Software License Agreement                                                   *
*                                                                              *
* The software supplied herewith by Microchip Technology Incorporated (the     *
* "Company") is intended and supplied to you, the Company's customer, for use  *
* soley and exclusively on Microchip products.                                 *
*                                                                              *
* The software is owned by the Company and/or its supplier, and is protected   *
* under applicable copyright laws. All rights are reserved. Any use in         *
* violation of the foregoing restrictions may subject the user to criminal     *
* sanctions under applicable laws, as well as to civil liability for the       *
* breach of the terms and conditions of this license.                          *
*                                                                              *
* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER    *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED        *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO  *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR    *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.     *
********************************************************************************
*
* Macromodel for the MCP6001/2/4 op amp family:
*   MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004
*
* Revision History:
*   REV A: 21-Jun-02, Created model
*   REV B: 16-Jul-02, Improved output stage
*   REV C: 03-Jan-03, Added MCP6001
*   REV D: 19-Aug-06, Added over temperature, improved output stage, 
*                     fixed overdrive recovery time
*   REV E: 27-Jul-07, Updated output impedance for better model stability w/cap load
*   REV F: 09-Jul-12, Added MCP6001R, MCP6001U
*
* Recommendations:
*   Use PSPICE (other simulators may require translation)
*   For a quick, effective design, use a combination of: data sheet
*     specs, bench testing, and simulations with this macromodel
*   For high impedance circuits, set GMIN=100F in .OPTIONS
*
* Supported:
*   Typical performance for temperature range (-40 to 125) degrees Celsius
*   DC, AC, Transient, and Noise analyses.
*   Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
*     open loop gain, voltage ranges, supply current, ... , etc.
*   Temperature effects for Ibias, Iquiescent, Iout short circuit 
*   current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
*   Some Variation in specs vs. Power Supply Voltage
*   Monte Carlo (Vos, Ib), Process variation
*   Distortion (detailed non-linear behavior)
*   Behavior outside normal operating region
*
* Input Stage
V10  3 10 -500M
R10 10 11 6.90K 
R11 10 12 6.90K 
C11 11 12 0.2p
C12 1  0 6.00P 
E12 71 14 POLY(4) 20 0 21 0 26 0 27 0   1.00M 20.1 20.1 1 1
G12 1 0 62 0 1m 
M12 11 14 15 15 NMI L=2.00U W=42.0U
M14 12  2 15 15 NMI L=2.00U W=42.0U
G14 2 0 62 0 1m 
C14  2  0 6.00P 
I15 15  4 50.0U
V16 16  4 -300M
GD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1)) 
V13  3 13 -300M
GD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1)) 
R70 1 0 20.6T  
R71 2 0 20.6T 
R72 1 2 20T 
I80 1 2 0.5p
*
* Noise, PSRR, and CMRR
I20 21 20 423U
D20 20  0 DN1
D21  0 21 DN1
G26  0 26 POLY(1) 3 4   110U -49U
R26 26  0 1
G27  0 27 POLY(2) 1 0 2 0   -440U 39.7U 39.7U
R27 27  0 1
*
* Open Loop Gain, Slew Rate
G30  0 30 POLY(1) 12 11   0 1
R30 30  0 1K
G31  0 31 POLY(1) 3 4 86 5.25
R31 31  0 1 TC=2.8m
GD31 30 31 TABLE {V(30,31)} ((-11,-1)(-10,-10n)(0,0)(1m,1000))
G32 32  0 POLY(1) 3 4 113.7 3.5
R32 32  0 1 TC=2.65m
GD32 30 32 TABLE {V(30,32)} ((-1m,-1000)(0,0)(10,10n)(11,1))
G33 0 33 30 0 1m
R33 33 0 1k
G34  0 34 33 0 425M
R34  34 0 1K
C34  34 0 74U
G37  0 37 34 0 1m
R37  37 0 1K
C37  37 0 41.6P 
G38  0 38 37 0 1m
R38  39 0 1K
L38  38 39 100U
E38  35 0 38 0 1
G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(16,1n))(16.1,1))
G36 33 0 TABLE {V(35,4)} ((-16.1,-1)((-16,-1n)(0,0)(1,1n))
*
* Output Stage 
R80 50 0 100MEG
G50 0 50 57 96 2
R58 57  96 0.50
R57 57  0 750
C58  5  0 2.00P
G57  0 57 POLY(3) 3 0 4 0 35 0   0 0.67M 0.67M 1.5M
GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
E55 55  0 POLY(2) 3 0 51 0 -0.7m 1 -40.0M
E56 56  0 POLY(2) 4 0 52 0 1.2m 1 -37.0M
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))
GD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) 
G53  3  0 POLY(1) 51 0  -49U 1M
G54  0  4 POLY(1) 52 0  -49U -1M
*
* Current Limit 
G99 96 5 99 0 1 
R98 0 98 1 TC=-2.8M,2.63U 
G97 0 98 TABLE { V(96,5) } ((-11.0,-10.0M)(-1.00M,-9.9M)(0,0)(1.00M,9.9M)(11.0,10.0M)) 
E97 99 0 VALUE { V(98)*((V(3)-V(4))*359M + 310M)} 
D98 4 5 DESD 
D99 5 3 DESD 
*
* Temperature / Voltage Sensitive IQuiscent
R61 0 61 100 TC 3.11M 4.51U
G61 3 4 61 0 1
G60 0 61 TABLE {V(3, 4)} 
+ ((0,0)(900M,0.0106U)(1.00,0.20U)(1.3,0.63U)
+ (1.5,0.66U)(1.6,1.06U)(5.5,1.10U))
*
* Temp Sensitive offset voltage 
I73 0 70 DC 1uA 
R74 0 70 1 TC=2 
E75 1 71 70 0 1 
*
* Temp Sensistive IBias 
I62 0 62 DC 1uA 
R62 0 62 REXP 58.2u 
* Voltage on R62 used for G12, G14 in input stage
*
* Models
.MODEL NMI NMOS
.MODEL DESD  D   N=1 IS=1.00E-15 
.MODEL DL  D   N=1 IS=1F 
.MODEL DN1 D   IS=1P KF=146E-18 AF=1
.MODEL REXP RES TCE=10.1 
.ENDS MCP6001

And here my schematic enter image description here

I guess there is something wrong with the model, but I am not expert in spice to solve it. Thank you in advance,

\$\endgroup\$
10
  • \$\begingroup\$ It seems to me you swapped in+ and in- \$\endgroup\$ Feb 13, 2017 at 12:47
  • \$\begingroup\$ nope, I tried both ways (swap In+ and In-) and the same result error. However, I used notation from original Microchip file. \$\endgroup\$
    – orfruit
    Feb 13, 2017 at 13:04
  • \$\begingroup\$ Sorry, my bad, that's a PMOS, polarity is correct. \$\endgroup\$ Feb 13, 2017 at 13:08
  • \$\begingroup\$ only the Microchip files are not working, I tried the same import with TI's OA, ST and others. Suspect that in spice file is the problem but I don't know what is wrong. \$\endgroup\$
    – orfruit
    Feb 13, 2017 at 13:32
  • \$\begingroup\$ Well, can you tell my why your PMOS is wrongly connected? \$\endgroup\$
    – G36
    Feb 13, 2017 at 16:03

3 Answers 3

1
\$\begingroup\$

Your not guaranteed that a model from any manufacturer is going to work (and most of models only simulate some of the aspects of a device. (for example: an op amp model may only simulate noise, common mode and input bias current and output current)

I would try validating only the model and run some tests (like .ac tests for bandwidth, a sin sweep in inverting gain, non inverting gain and unity gain) just to see how the model behaves. Then if you throw the model into a different circuit you know it will work.

Secondly there are different solvers that can be changed in the control panel Try a different solver and see if it gives you better results, some solvers work better than others for a given circuit.

Don't change the tolerances unless read up on it first.

enter image description here

\$\endgroup\$
2
  • \$\begingroup\$ I tried, no luck :( Also tried Trtol = 7, but thanks for guide! \$\endgroup\$
    – orfruit
    Feb 14, 2017 at 8:14
  • \$\begingroup\$ I cannot vote but I gave ok, thank you! \$\endgroup\$
    – orfruit
    Feb 15, 2017 at 8:01
2
\$\begingroup\$

Hmm.. I found it :) In case anyone struggle like me. Not sure how would impact my simulation, but adding extra option to LtSpice at least started simulation:

.options cshunt = 1e-13

However, simulation is horrible slow :(

\$\endgroup\$
2
  • 1
    \$\begingroup\$ That adds capacitors to EVERY node, and basically smooths out numerical noise. In some simulations I have added small pF capacitors to certain (like the output of an opamp) or nodes that have numerical noise. \$\endgroup\$
    – Voltage Spike
    Feb 14, 2017 at 16:40
  • \$\begingroup\$ Ok that saved me. Did you find the solution somewhere in the web? I want to know more about why it needs that option to run properly \$\endgroup\$ Mar 31, 2021 at 20:24
0
\$\begingroup\$

Old thread but the question remains. I had the same issue and finally I solved my own issue. I post my findins here in case it helps anyone else googling the issue.

NOTE: This applies only to issues related to "Initial timepoint" Short answer, try:

  1. Check "Start external DC supply voltages at 0V"
  2. Un-check "Skip initial operating point solution"

enter image description here

Why does this help? My guess is that the problem is two-fold.

a. If you cannot find a stable operating point (self-oscillating circuits may not have a stable operating point) you must "Skip initial op point".

b. Without a stable op-point all capacitors and coils are initiated at 0V and 0A. Then applying supply-voltages as a step at the initial timepoint may cause numerical problems

But when using "Start external DC supply voltages at 0V" the self-oscillating cirtuits will not oscillate and an operating point can be found. And because the voltage sources are applied as a ramp (default during 20us) there will be no infinite derivates and the simulation seems to work much more stable.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.