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I'm building my first PCB design using EasyEDA tool and I have some concerns to avoid errors after printing. Here is my circuit (I hope it's clear enough):

enter image description here

I'd like to know are the spacing between the components okay enough or not (each grid block is 0.1*0.1 inches).

I also want to know, is it okay to have the labels on top of the wires?

I've used DIP8 IC's, when it's printed can I put an IC socket first then mount my IC on it or should I change my design to have 8 pin IC sockets instead of my original ICs.

Finally, what is the best way to check it for errors before sending it to be printed?

The dimension of the board are (3.0315*2.019685 inches) Thanks

EDIT: I took your tips and rearranged the circuit to reduce the tracks' length. I also added the capacitors near the IC's. The supply tracks width were doubled as well.

EDIT2: I increased the clearance and the track width for all of them. I also changed the pads' shape for the IC to have bigger pad size.It looks better now.

Edit3: RG (10k) is now closer to the amplifiers.

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    \$\begingroup\$ Why have you got the 10k1, 10k2 and 10k3 so far away from the obvious connections on the chips? \$\endgroup\$ – Andy aka Feb 14 '17 at 9:52
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    \$\begingroup\$ What components are used for the DIP8 packages marked with C1..C4? The C designator is commonly used for capacitors and I suspect those are not capacitors. Furthermore a hint: Put capacitors (100 nF) between the supply voltages of your amplifiers for each amplifier close to the package. That will stabilize their supply and thus performance. \$\endgroup\$ – Grebu Feb 14 '17 at 10:05
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    \$\begingroup\$ Generally you place the components to minimize track lengths rather than arranging them by type. Longer traces mean more opportunity for noise to get picked up. What you have done may make hand assembly easier but results in a circuit that doesn't work as well. Since you only have to built it once a little more hassle building it is normally considered worth it in order to improve performance. \$\endgroup\$ – Andrew Feb 14 '17 at 10:42
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    \$\begingroup\$ And ideally 1 cap per IC on the power/GND connections, you can sometimes bend those rules if the trace lengths are short, things are all low speed and you don't mind a little bit of noise. You may also want to thicken up the power traces, you have plenty of space so there is no harm in making them a little thicker. \$\endgroup\$ – Andrew Feb 14 '17 at 10:43
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    \$\begingroup\$ You normally put the designations of the parts (for example R17) on the board. Values are in the bill of materials. You go to place R17, look in the BOM and see 1MOhm, and place a part of that value for R17. The way you have done it will cause you to pull your hair out if you have to change values in your schematic diagram. You will have to change the designation, and change the silkscreen. \$\endgroup\$ – JRE Feb 14 '17 at 11:30
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It looks fine in terms of spacing between components.

The labels you mention, I assume that this is the silk screen for components ID etc? If so, then that can be anywhere, it will not affect the circuit, so that is fine.

Of course if you use DIP8 IC's you can put an IC socket in there before mounting the IC, that is not a problem.

The best way to check for errors is to do a DRC (Design Rule Check) which should highlight any errors in the layout. I have not used EasyEDA before so I do not know where it is but in most design software packages it is pretty easy to find

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  • \$\begingroup\$ Yes that's on the silk layer, It does the Design Rule Check, but I found some errors even with that. I had to manually compare the schematic and PCB layout, because some wires were not connected properly in the schematic. (That was a human error I know, that's what I wan't to avoid)....... Thank you very much. \$\endgroup\$ – Isra Feb 14 '17 at 10:09
  • \$\begingroup\$ If there are errors in the DRC, then those will have to be fixed before you send it to be printed. As long as you see them and fix them, you should be good. I looked aswell at the tips from Andrew and it may be a good idea to increase power trace width and add some 100nF decoupling caps on the ICs too. Human errors will happen, it's just about recognising them and solving them and in time, they will happen less often. \$\endgroup\$ – MCG Feb 14 '17 at 11:22
  • \$\begingroup\$ "then that can be anywhere" ... Not quite. In general, silkscreen should not be placed over bare copper. It may be subject to damage from heat due to soldering processes or in some cases circuit operation. Not really an issue here assuming the board is ordered with solder-mask. This was a mistake I once made and was alerted by the board house. This is even more important for SMT boards that are reflow soldered. \$\endgroup\$ – Tut Feb 15 '17 at 12:27
  • \$\begingroup\$ @Tut - I did assume there would be a solder mask as that is generally the way it goes. \$\endgroup\$ – MCG Feb 15 '17 at 14:22
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Increase clearance above DRC minima wherever it is sensibly easy to do so.

Some tracks pass far closer to pads than is necessary and will probably cause problems if hand soldering.

Track to track clearances are insanely small at top left with no apparent reason.

Increase track widths modestly if sensibly easy to do. Small width tracks invite fabrication errors and are extremely easy to damage by heat transfer if hand soldering.

Make IC and other pad sizes sensibly large - increase sizes along length dimension of IC at cost of pad-pad clearance - but not TOO close, and if possible increase sizes laterally as well. eg your pin 1 IC pads are MUCH more likely to survive hand soldering than the other IC pads.

Component to component lateral spacings is based on body sizes. You can test this with vero /vector/pad board and see how close they are at various spacings - or use manufacturers footprints.

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  • \$\begingroup\$ I did what you suggested and edited the post. As you can see it's much better that before. Regarding the component to component spaces, I didn't understand the vero/vector/pad board point, what do you mean? Thanks very much. \$\endgroup\$ – Isra Feb 15 '17 at 4:26
  • \$\begingroup\$ @Isra I meant that if you mount the actual components on prepunched board which has spacing of (usually) 0.1" you can see what body clearances you actually achieve in practice. egif you mount the at 0.3" centres and have a measured 0.15" body to body clearance then you cou;d reduce separation to 0.2" centres and have 0.05" clearances. If at 0.3" c-c you had say 0.1" clearance you could change to 0.25" c-c and have 0.05" clarances. How small a clearance is acceptable depends on your requirements. ... \$\endgroup\$ – Russell McMahon Feb 15 '17 at 5:41
  • \$\begingroup\$ ... [I've seen systems with negative clearances - with every second component mounted with greater than usual above board spacing so bodies do not touch :-).] \$\endgroup\$ – Russell McMahon Feb 15 '17 at 5:42

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