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Question: Is Quad SPI really a serial interface, a parallel interface or both?

The image below depicts that independent databyte may not be able to send over individual lines (I see databits spread over multiple lines) making them "not 4 independent serial interface".
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Another image from STM MCU below.
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last snapshot of serial interface tag in EE.SE
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EDIT: The question here is different from mine. The question deals with the different topologes of SPI while my question is on Quad SPI in particular and to identify clearly the interface nomenclature.

It is only to gain better understanding on how we classify the serial and parallel interface in case of Quad SPI. This is a discussion which has arised many times but could not be answered well enough by me.

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    \$\begingroup\$ Who wants to know? It seems that this type of interface has characteristics of both serial and parallel, but it is predominantly serial because it takes more than one clock cycle to complete. \$\endgroup\$ – Sean Houlihane Feb 14 '17 at 10:27
  • \$\begingroup\$ @SeanHoulihane only me atleast. I want to know is there a gray area w.r.t. classification of Quad SPI as serial or parallel. it is just in my head for long time and i would like to deal with it. \$\endgroup\$ – User323693 Feb 14 '17 at 10:35
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    \$\begingroup\$ Possible duplicate of What is dual/quad I/O? \$\endgroup\$ – m.Alin Feb 14 '17 at 10:36
  • \$\begingroup\$ What about a parallel printer port - if you look at it from the perspective of transmitting a whole page of characters to a printer, you could see it as 8 serial comms streams. \$\endgroup\$ – Andy aka Feb 14 '17 at 11:34
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    \$\begingroup\$ It is, indeed, a gray area. Some will say "it is obviously serial", some others will say "it is obviously parallel". Others, like me (and @Sean, it seems), will say "who cares?". This is just a naming problem. \$\endgroup\$ – dim Feb 14 '17 at 11:46
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Quad SPI is a 4 bit wide parallel bus.

4 independent serial interfaces would require 4 independent clocks.

However since it's designed to be compatible with standard SPI and acts purely as a way to boost the SPI data rate it is a bit of an in between technology, it has features of both interfaces.

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    \$\begingroup\$ what I understand from your answer is that, though the Quad SPI is parallel interface, only for historical reason we call it, as SPI (Serial Peripheral Interface). hope i am right. \$\endgroup\$ – User323693 Feb 14 '17 at 10:43
  • \$\begingroup\$ It has, however, much in common with the classic SPI: /CS signal, clock phase and polarity, so it's also an SPI interface with 3 extra data lines if you will. No way to uniquely classify it. Suggestion: Just call it "Serial/Parallel Interface" ;-) \$\endgroup\$ – JimmyB Feb 14 '17 at 10:48
  • \$\begingroup\$ @JimmyB that's an interesting suggestion too to have it as both \$\endgroup\$ – User323693 Feb 14 '17 at 11:05
  • \$\begingroup\$ OTOH, it's not full duplex anymore, which is an essential characteristic of SPI with its dedicated MOSI and MISO lines. \$\endgroup\$ – JimmyB Feb 14 '17 at 11:36
  • \$\begingroup\$ @JimmyB I agree with you. I think, i should then leave the topic as "classified" and continue into others which matter. But, i will get back on it some time ;) \$\endgroup\$ – User323693 Feb 14 '17 at 12:03

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