Can anyone please explain me about the red dots in the picture

I saw the picture some where and wondering if the red dots are buried vias or test points

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    \$\begingroup\$ Looks like test points on the other side of PCB taken via via \$\endgroup\$ – Umar Feb 14 '17 at 12:43
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    \$\begingroup\$ Buried vias are just that: buried, they would not be visible here. \$\endgroup\$ – Bimpelrekkie Feb 14 '17 at 12:44
  • \$\begingroup\$ @m.Alin but they appear in meandered lines; I don't have a great feeling when combining controlled-length lines with inductive elements (vias). Also, blind guess, U2100 and U2000 look like DRAM, and why would you need vias to another layer in a CPU-RAM link? \$\endgroup\$ – Marcus Müller Feb 14 '17 at 12:48
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    \$\begingroup\$ The red dots can't be test points since they are covered by solder mask (that's why they are red). \$\endgroup\$ – Olin Lathrop Feb 14 '17 at 12:53
  • \$\begingroup\$ Possibly copper filled micro-vias. \$\endgroup\$ – Peter Smith Feb 14 '17 at 14:44

The red dots definitely have the same shape and size as the showing pads for TP4003 and TP4003. The ones that are red are covered with the solder mask and thus the reason that they appear in the red color!!

It is likely that the original PC board artwork designer placed test points on every net of the board and then later modified the solder mask to cover those not needed on finished assemblies. There are several pairs of covered test point pads in the lower right corner of the picture that even have silk screen indicators as test points that support this guess.

Some bare board manufacturing facilities may make use of all these test points to electrically check a raw, in process, board for shorts before committing it to later stages of fabrication. In the early manufacturing stages these pads would not yet be covered with the solder mask. This can lower overall fallout at the finished board test station, especially for cases where there are a lot of layers involved in the board stackup. Such in process testing may also apply for testing buried via layers as well.

  • \$\begingroup\$ Thanks Michael, But it looks like DDR chips, Is it possible to place test points on the lines and if you observe there are red dots even on the differential pair. So my question is it a good practice to have test points on the high speed signals like DDR?? I am new to the field, Kindly bear with me. \$\endgroup\$ – pavan Feb 15 '17 at 4:28

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