Consider the current mirror below. As you can see, the circuit is affected by a threshold voltage mismatch, modelled by \$ V_{mm} \$. I want to minimize the effect of the mismatch and dimension the circuit accordingly.

So from my point of view, what needs to be done is adjusting the length of the MOSFETs, because of the short-channel effect, which causes a decrease of threshold voltage by lowering the length. Since \$ V_{mm} \$ is unknown, it is impossible to design the length in a way that the mismatch would be compensated. Therefore, the best thing would be to increase the length of both transistors to increase their threshold voltage, until the short-channel effect is not noticeable anymore. Then, a mismatch would have the smallest effect on the circuit.

Is my above reasoning correct? Is there anything else I can do to diminish the effect of mismatch?


simulate this circuit – Schematic created using CircuitLab

EDIT: Concerning the influence of the effective channel length on the threshold voltage:

An interesting phenomenon observed in scaled transistors is the dependence of the threshold voltage on the channel length. As shown in Fig. 17.5, transistors fabricated on the same wafer but with different lengths yield lower V TH as L decreases. This is because the depletion regions associated with the source and drain junctions protrude into the channel area considerably, thereby reducing the immobile charge that must be imaged by the charge on the gate (Fig. 17.6). In other words, part of the immobile charge in the substrate is now imaged by the charge inside the source and drain areas rather than by the charge on the gate. As a result, the gate voltage required to create an inversion layer decreases. Since the channel length cannot be controlled accurately during fabrication, this effect introduces additional variations in V . The implication of this phenomenon in analog design is that if the length of a device is increased so as to achieve a higher output impedance, then the threshold voltage also increases by as much as 100 to 200 mV. [Razavi]

  • \$\begingroup\$ which causes a decrease of threshold voltage by lowering the length The threshold voltage does NOT depend on the dimensions of the MOSFET. \$\endgroup\$ – Bimpelrekkie Feb 15 '17 at 11:22
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    \$\begingroup\$ For best matching you want to minimize short channel effects so a large L is always needed. In general a larger area is always beneficial for matching so make both L and W larger. Also you want Vt (threshold voltage) variations to have a small influence, that is done by making W/L smaller (W smaller, L larger) which increases Vgs so Vt gets smaller relative to Vgs. \$\endgroup\$ – Bimpelrekkie Feb 15 '17 at 11:31
  • \$\begingroup\$ @FakeMoustache Thanks for the comment! Why is making W/L smaller increasing Vgs? Is it because the resistance is increasing? Btw, have a look at my first EDIT, where the influence of the effective channel length on the threshold voltage is discussed. \$\endgroup\$ – Daiz Feb 15 '17 at 11:54
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    \$\begingroup\$ Why is making W/L smaller increasing Vgs Look at the formula for Id in saturation: Id = W/L K (Vgs-Vt)^2 For the same Id Vgs will need to increase when W/L decreases. \$\endgroup\$ – Bimpelrekkie Feb 15 '17 at 12:24

How to minimize threshold voltage mismatch of a current mirror?

I want to minimize the effect of the mismatch ...

minimizing the mismatch and minimizing the effect of the mismatch are two different things.

for the former, no choice other than a different topology, pre-selection / classification of transistors before putting them in a circuit, or in the case of an IC, process uniformity.

for the latter, more options are available, like degeneration.

You probably want to pick one of the two for a more in-depth discussion.

  • \$\begingroup\$ Thanks for the hint, I definitely meant that I want to minimize the effect of the mismatch, I said it wrong in the title (changed it). It would be great if you could give me feedback to my above reasoning, as well as elaborate what improvments can be done. \$\endgroup\$ – Daiz Feb 15 '17 at 11:44

Your reasoning is correct. However you have to take into account that by increasing L (or decreasing W), overdrive voltage will increase for a fixed Id current value.

In circuit where the current consumption is determined by a current mirror (classical differential pair, for example), a big current mirror Vod will reduce your output voltage swing.

There is normally a trade-off between the "quality" of the mirror and the Vod voltage. In terms of design, the inversion coefficient of a current mirror should be set to approximately 10, which is translated in a Vod of 200 mV.


You can shift the threshold voltage, or effective gate voltage. Firstly, let's look at the current equation (EKV unified):

$$I_{f,r} =\frac{W}{L}2 U_{T}^2\frac{\mu C_{ox}}{ \kappa}\ln^2 \left[1 + e^{\left({\kappa\left(V_g-V_{T0}\right) - V_{s,d}}\right)/\left({2 U_{T}}\right)} \right]$$

If you want to change the threshold mismatch, you can: make \$W/L\$ very large, move \$V_{T0}\$ in some manner, or move \$V_S\$. Assuming that you do not have FAB access, I would just put two FETs at the sources of the currently existing nFETs, and then set their currents with separate bias voltages. This will move \$V_S\$ on the devices so that you can match them. In your image, \$V_{ss}\$ is just tweaking the offset between the two thresholds, but in practice, that would be hard due to noise.

  • \$\begingroup\$ One addendum, you cannot change W/L on an aggressive process. I just add cells until I have a HUGE common centroid field to create effective W/L ratios for analog FETs. \$\endgroup\$ – b degnan Feb 15 '17 at 11:55
  • \$\begingroup\$ Aggressive Processes do not allow large gate-area FETs? Are those not called "gate capacitors"? Smallest geometry I've used is 0.25 micron. \$\endgroup\$ – analogsystemsrf Feb 15 '17 at 13:59
  • \$\begingroup\$ @analogsystemsrf The last process that I used where I could change the W/L of the gate was 65nm. At 32SOI and 14nm, I have a fixed gate size as a cell. To make things worse on FinFETs, I have two fins per gate, with threshold mismatch. My amplifiers that I use to make voltage references are just crazy in area. There's so much metal that I do not need feedback capacitors just to the parasitics. \$\endgroup\$ – b degnan Feb 15 '17 at 14:41
  • \$\begingroup\$ Any 1micron^2 W*L FETs? Those would be "long-channel". How does that Vt differ from the 14nm Vt? \$\endgroup\$ – analogsystemsrf Feb 15 '17 at 14:53
  • \$\begingroup\$ @analogsystemsrf There are no real "long channel" devices, so you end up with tiled FET closest to the "drain" acting as a cascode. I see the Vt spread to be +-100mV on a 800mV process; however, by the time you make a common centroid, you end up +-10mV. For my devices that need to be precision, I generally have some method of tweaking this, but I have found it to be more fruitful to just design circuits that are robust to mismatch instead of getting rid of it. \$\endgroup\$ – b degnan Feb 15 '17 at 15:21

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