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There are 3 stages that every VHDL program undergoes: parsing, analysis and elaboration. Elaboration is circuit instantiation once top entity is specified. Analysis is something that determines available entities. What is it actually?

It is probably applied computer science question, but I see the vhdl tag specified here.

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  • \$\begingroup\$ Read "Semantic Analysis" in any book on compiler design. \$\endgroup\$ – Brian Drummond Feb 15 '17 at 14:33
  • \$\begingroup\$ @BrianDrummond Soulds like a good answer. \$\endgroup\$ – Val Feb 15 '17 at 15:44
  • \$\begingroup\$ IEEE Std 1076-2008 13. Design units and their analysis, 13.1 Design units Analysis of a design unit defines the corresponding library unit in a design library. Think object files, although those libraries can be directly in memory for some implementations. \$\endgroup\$ – user8352 Feb 15 '17 at 19:32
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Analysis is the process where the design files are checked for syntactic and semantic errors. The syntactic rules are dictated by the language. On VHDL, if you write IF but forget to include the THEN clause, that is a violation of the syntax, the set of rules of the VHDL language.

Semantics are the meaning of the language. As an example, a sentence describing an addition is tagged as incorrect if the operands are of incompatible types because the VHDL compiler cannot resolve the meaning of that sentence.

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  • \$\begingroup\$ It seems that you say the same as Roman, that Analysis involves the parsing. Thanks anyway. \$\endgroup\$ – Val Mar 2 '17 at 19:18
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Where did you heard about these three stages? I think two of these parsing and analysis are the compilation of code. And in this step compiler checks syntax and building a representation of the code which could be read in the next step by your tool.
So analysis maybe the same or part of compilation, I mean in this step your tool does syntax checking and etc.

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