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I've had some experience with FPGA/HDL tool suites such as Xilinx ISE, Lattice Diamond, etc. The general workflow is writing Verilog/VHDL, simulation, testing and then programming the FPGA.

I've heard a couple of people say ASIC design is very different. What are the toolsets used for the two major types of ASICs, Gate level ASICs and Transistor level ASICs? I've been looking into High Level Synthesis tools such as Catapult C and Cadence C to Silicon, but I've never tried any yet. Can you explain the different types of tools available in the ASIC/FPGA field that can change/speeden up the typical HDL workflow?

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Typically ASIC design is a team endeavor due to the complexity and quantity of work. I'll give a rough order of steps, though some steps can be completed in parallel or out of order. I will list tools that I have used for each task, but it will not be encyclopedic.

  1. Build a cell library. (Alternatively, most processes have gate libraries that are commercially available. I would recommend this unless you know you need something that is not available.) This involves designing multiple drive strength gates for as many logic functions as needed, designing pad drivers/receivers, and any macros such as an array multiplier or memory. Once the schematic for each cell is designed and verified, the physical layout must be designed. I have used Cadence Virtuoso for this process, along with analog circuit simulators such as Spectre and HSPICE.

  2. Characterize the cell library. (If you have a third party gate library, this is usually done for you.) Each cell in your library must be simulated to generate timing tables for Static Timing Analysis (STA). This involves taking the finished cell, extracting the layout parasitics using Assura, Diva, or Calibre, and simulating the circuit under varying input conditions and output loads. This builds a timing model for each gate that is compatible with your STA package. The timing models are usually in the Liberty file format. I have used Silicon Smart and Liberty-NCX to simulate all needed conditions. Keep in mind that you will probably need timing models at "worst case", "nominal", and "best case" for most software to work properly.

  3. Synthesize your design. I don't have experience with high level compilers, but at the end of the day the compiler or compiler chain must take your high level design and generate a gate-level netlist. The synthesis result is the first peek you get at theoretical system performance, and where drive strength issues are first addressed. I have used Design Compiler for RTL code.

  4. Place and Route your design. This takes the gate-level netlist from the synthesizer and turns it into a physical design. Ideally this generates a pad-to-pad layout that is ready for fabrication. It is really easy to set your P&R software to automatically make thousands of DRC errors, so not all fun and games in this step either. Most software will manage drive strength issues and generate clock trees as directed. Some software packages include Astro, IC Compiler, Silicon Encounter, and Silicon Ensemble. The end result from place and route is the final netlist, the final layout, and the extracted layout parasitics.

  5. Post-Layout Static Timing Analysis. The goal here is to verify that your design meets your timing specification, and doesn't have any setup, hold, or gating issues. If your design requirements are tight, you may end up spending a lot of time here fixing errors and updating the fixes in your P&R tool. The final STA tool we used was PrimeTime.

  6. Physical verification of the Layout. Once a layout has been generated by the P&R tool, you need to verify that the design meets the process design rules (Design Rule Check / DRC) and that the layout matches the schematic (Layout versus Schematic / LVS). These steps should be followed to ensure that the layout is wired correctly and is manufacturable. Again, some physical verification tools are Assura, Diva, or Calibre.

  7. Simulation of the final design. Depending on complexity, you may be able to do a transistor-level simulation using Spectre or HSPICE, a "fast spice" simulation using HSIM, or a completely digital simulation using ModelSim or VCS. You should be able to generate a simulation with realistic delays with the help of your STA or P&R tool.

Starting with an existing gate library is a huge time saver, as well as using any macros that benefit your design, such as memory, a microcontroller, or alternative processing blocks. Managing design complexity is a big part as well - a single clock design will be easier to verify than circuit with multiple clock domains.

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    \$\begingroup\$ Since you mentioned Virtuoso, Cadence provides a complete toolchain for the design (I think it's called Opus), where it's possible to start from the schematics, layuot the single cell, evaluate the parasitic effects, characterise it and then build it into the upper level. \$\endgroup\$ – clabacchio Mar 25 '12 at 9:46
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    \$\begingroup\$ I think every major vendor offers a complete toolchain. We ended up using multiple vendors in our toolchain, and that way we could use the tools that we were most familiar with or had the best industry reputation. \$\endgroup\$ – W5VO Mar 25 '12 at 17:42
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    \$\begingroup\$ Picking tools for library or design kit support is practically a requirement. If you aren't using the supported version of a particular piece of software, some incompatibilities may kill your design or give you false readings. That being said, the vast majority of EDA tools I have seen run on Unix/Linux systems. Most have steep learning curves. \$\endgroup\$ – W5VO Mar 25 '12 at 22:26
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    \$\begingroup\$ @MartinThompson Absolutely. The more you push the boundaries of your technology (ASIC/FPGA) the more critical those steps are. That being said, the ASIC versions of those tools give you much more rope for you to get into trouble. \$\endgroup\$ – W5VO Mar 26 '12 at 14:30
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    \$\begingroup\$ Note that 1 and 2 are not a general part of design. These steps are a part of so-called "process qualification", and results (fully characterized libraries) are provided by FAB Vendor. But some companies are doing "full custom design", and must complete 1 and 2 on their own. \$\endgroup\$ – Ale..chenski Sep 18 '16 at 1:28
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The answer from W5VO tends to focus on the back-end, and this is a major difference between ASIC and FPGA flows; but it misses out the digital design verification part.

When getting a design onto silicon can cost a million dollars and more, and you can pack many more usable gates on an ASIC compared to an FPGA, then you spend a lot more time away from the lab and PCB's in front of workstations running simulator farms and emulators and writing tests to more fully verify an ASIC design before you release it for production. FPGA designers tend to do a large part of their testing by using the FPGA in the system it will become part of.

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  • \$\begingroup\$ I would add that the basic workflow for a digital designer is not much different between ASIC and FPGA, but ASIC has much more flexibility in terms of available macro/micro elements, placing and routing, while FPGA is restricted to their pre-fabricated logic blocks and limited in interconnect topology. Thus FPGA can't reach performance levels of ASIC, and may dictate slightly different design solutions. \$\endgroup\$ – Ale..chenski Sep 18 '16 at 1:40
  • \$\begingroup\$ Hi Ali Chen. If digital design and digital verification are thought of as being separate then the flow for purely digital design is closer for FPGA vs ASIC, but there is great separation in the verification as I mentioned. :-) \$\endgroup\$ – Paddy3118 Sep 20 '16 at 13:27

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