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I look into the D-Type Flip Flop, so I checked it and found some logical diagrams, but they were all differents...

I have no idea what this gate do :

-Does it switch Q and /Q depending of the state of the clock and the activation of the other input :

Clock -> made the states switch only if the other input is true.

-Does if switch Q and /Q depending of the sate of the other input and refresh the output when the clock is true :

Input -> change the state depending on the input value, refresh the output when clock is true

So which one must I follow ?

enter image description here

Another diagram ?

here is what I get :

enter image description here

first one change the output depending of the clock state; the 2 other change their output depending on the input value. Refresh depending of the value of the clock.

Thanks,

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  • \$\begingroup\$ read through electronics-tutorials.ws/sequential/seq_4.html The internal structure of a D flip flop or the technology used is less important than what it does. \$\endgroup\$ – JIm Dearden Feb 16 '17 at 12:39
  • \$\begingroup\$ The first image you posted is not a D flipflop its a D latch which is a level triggered device not an edge triggered. IF(CLK==1) OUT=in; Else OUT=OUT; you should use the term Gate instead of clock usually clock is used when talking about FF \$\endgroup\$ – Elbehery Feb 16 '17 at 13:24
  • \$\begingroup\$ Unlike the 2nd image which is for a D flip flop. If(CLK.RISING) OUT=IN; Else OUT=OUT; so both images represents two different things \$\endgroup\$ – Elbehery Feb 16 '17 at 13:36
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A D Flip Flop will track its input 'D' in function of the clock. 'D' in this case stands for Data. Note that as shown in the picture below, the output 'Q' is only toggled high or low depending on the clock signal. Usually, a true value (1 or high) will trigger the input. If D goes high and the clock is low, it will wait until the rising edge of the clock to trigger Q high. So in general there are a few things to remember about a D Flip Flop:

  • The output Q and /Q are only triggered in function of the clock
  • It can be thought of as a memory cell
  • It is also named a bistable multivibrator
  • Memory units could have thousands/millions of flip flop tied together
  • A basic shift register can be made out of D Flip Flops

enter image description here

Finally, the picture below summarize essentially what I am trying to explain. A Flip Flop is clock triggered, and the output will follow the input upon a clock trigger.

enter image description here

Look into D Latch if you are looking at a Flip Flop that would be "level sensitive" and D Flip Flop if you want something that is "edge sensitive". The output Q will only depend on the clock state and the input.

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  • \$\begingroup\$ I think there is something wrong with your diagram: Why are the first 0-->1 and the last 1-->0 transition of Q not happening at rising CLK? \$\endgroup\$ – Curd Feb 16 '17 at 13:17
  • \$\begingroup\$ @Curd I do not see what you are referring to? Clock diagram or truth table? I revised clock sequence and Q is triggered on rising edge every time. It holds its state if D is still high or still low. \$\endgroup\$ – 12Lappie Feb 16 '17 at 14:18
  • \$\begingroup\$ I mean the waveform diagram. Look at first 0-->1 transition of Q or last 1-->0 transition of Q. There is no rising CLK. \$\endgroup\$ – Curd Feb 16 '17 at 14:30
  • \$\begingroup\$ BTW: I have also a problem with your truth table. It repesent rather a latch (level sensitive) not a D-FF (edge sensitive). \$\endgroup\$ – Curd Feb 16 '17 at 14:39
  • \$\begingroup\$ @Curd I edited the answer. You are right, I had a D Latch shown in the picture which is "level-sensitive" and not "edge-sensitive". \$\endgroup\$ – 12Lappie Feb 16 '17 at 14:50

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