I want to interface an ASIC with a SAR ADC, e.g. LTC2323-14 (5MHz, 14 bit). The timing diagram looks as follows:

enter image description here

I would like to generate the control signals (i.e. CNV and SCK) with my ASIC, based from a master clock (e.g. 100 MHz).

The datasheet states:

  • tCNVH >= 25ns
  • tSCKL >= 4ns, tSCKH >= 4ns, tSCK >= 9.4ns
  • tCONV >= 171.5ns
  • tDCNVSCKL >= 9.5ns
  • tDSCKLCNVH >= 19.1ns

I am confused by this diagram: Do I need to turn off SCK while CNV is high? Do I even need to make sure that the first pulse does not appear after tDCNVSCKL after CNV goes down? This would make my clock generation extremely hard.

Or can I just leave on SCK all the time and the timing spec just means that I can expect B14 not before tDCNVSCKL?

In this case, I would just use a, say, 100 MHz clock as SCK input and derive CNV from this clock; e.g. creating a 3 period pulse (30ns) used as CNV.

Also, the DS states: "The typical pulse width of the CNV signal is 30ns at 5Msps conr rate" and "A 105 MHz external clock must be applied at the SCK pin to achieve 5Msps throughput".

I do not understand how exactly 105 MHz are obtained:

For 105 MHz, tSCK=9.524ns.

  • CNV takes at least 3 cycles to satisfy >25ns
  • The 15 data bits require 142.85714ns
  • tDCNVSCKL requires at least 1 cycle
  • tDSCKLCNVH requires at least 3 cycles.

Summing this up makes tTHROUGHPUT of 3+15+1+3=22 cycles or 105M/22=4.773 MHz < 5 MHz.

For the data this would be 15 cycles, tDCNVSCKL is one cycle, tDSCKLCNVH is three cycles.

  • \$\begingroup\$ Can't you use a gating mechanism, where the clocks will be allowed to pass only during the time of interest. The original click will be running independently all the time, but the ADC sees only what it has to? \$\endgroup\$
    – User323693
    Feb 17, 2017 at 0:48
  • 1
    \$\begingroup\$ I see, but then I have to create the gating clock too satisfying all the clock specs which just complicates. Hence my question whether this is not necessary ... \$\endgroup\$
    – divB
    Feb 17, 2017 at 1:13

1 Answer 1


I can answer the question now on my own: Yes, the timing is indeed that complicated, unfortunately. The problem is that running the clock at the sampling instant would corrupt the sample, hence it needs to be turned off.

Controlling such an ADC requires complicated logic that's best performed using an FPGA/microcontroller. The signals for this ADC example can be generated with an 110 MHz master clock and 22 cycles (which gives effectively 5 MHz).


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