# Understand the JK Flip Flop Logic Diagram

I'm actually looking for some explanation for the JK Flip Flop :

On a website : logic.ly I can simulate the behavior of logic gates, or logic circuit.

When I use the JK Flip Flop icon, it works as it must work. And when I look on the internet to get a logic diagram of the JK flip flop (to reproduce it using logic gate) I got undefined state for both output... So is something wrong with my diagram ? Does it come from the website ?

Here is the logic diagram I got from internet for the JK Flip Flop Here is the diagram I made on logic.ly, and I got multiple undefined states (red wire) whether the input are true or false (for each possible possition, clock down or up is the same) So if someone could tell me what's wrong and help me to solve that, it'll be really appreciated !

Thanks,

• This was already asked many times. The Flip Flop uses 'analog' features of the gates to work. In real world the Flip Flop is an unbalanced system, where a minor difference in the inputs to the gates is 'amplified' until the flip flop reaches a stable state. Many simulators don't model the gates at the level of complexity needed to get the results that you get in real life. Oscillators and other kinds of bistable or astable logic circuits are the Achilles heel of many simulators. – Claudio Avi Chami Feb 17 '17 at 20:31
• A solution could be to add a small voltage source somewhere in the circuit to force the simulator into a certain state, like Q = 1, QN = 0. Some simulators have a "nodeset" or "initial condition" setting which could do the same job. – Bimpelrekkie Feb 17 '17 at 20:34