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I always though that simulation of hardware architectures (FPGA/ASIC) cannot cover every possible stimulus and corner-case that can be encountered in real conditions, and that hardware-accelerated verification is needed to cover real use-cases.

However, a friend told me that this statement is wrong. Every transaction can be recorded and replayed during simulation. The only issue is that it would often take days or months to complete the simulation (like testing 10s of an H264 stream sent to a decoding IP).

This makes sense to me, but since we're both working in a lab research unit and not in an industry verification team, I wondered: is my friend right?

On a side note, it's quite unbelievable that this stackexchange site has no verification tag...

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    \$\begingroup\$ First: probably the lack of the tag is because there is a synonim. Probably what you are looking for is test or production-testing \$\endgroup\$
    – clabacchio
    Mar 26, 2012 at 7:29

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My experience comes from the world of FPGA design.

It has been my experience that you can functionally test everything in a design, but as your friend says, the length of the simulation becomes the real limiting factor. When I say functionally test, I mean a test that assumes correct timing of the design, and is not testing edge cases of variations in timing (i.e. assume Place and Route of your design targeting your device is correct). It can take hours/days to simulate a few seconds of an FPGA design. Which in a world where many things can be happening in parallel at 80-400MHz, it is a lot of operations to simulate.

However, the more critical it is that the design is right the first time, the more time you are willing to spend testing all of the cases, especially corners. As you mentioned, people will typically focus on exercising corner cases after they are fairly confident that "normal cases" are working correctly.

Hardware co-simulation can do a couple things. First, it can give you farm fuzzies that your design that worked in "pure simulation" also works in hardware. Second, it can greatly accelerate your verification, assuming you have a fast model to determine what exact output you are expecting for a given input.

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Amongst many other techniques, big design teams for critical hardware use coverage-based verification techniques to check that

  1. every bit of code that's been written gets tested by some test-case or other
  2. every bit of specification that requires some behaviour has that behaviour tested

This is done by a combination of carefully-designed stimulus, constrained random stimulus and coverage-driven stimulus tools (which analyse the results of coverage tests to see what's been missed and try and produce stimulus to "aim towards them")

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