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I need to step-up a clock signal of 8 MHz from 3.3V to 5V, I was wondering if this type of level shifter would work :
The BSD840N as rise and fall time fast enough for my application but I'm not sure I'm thinking this the way it should be thought. Is it correct to assume it will work in such a setup ?
The rising edges of your signal will be slowed down by the RC filter formed by the pullup and any parasitic capacitances in your circuit. Assuming those are 10 pF, you get a time constant of 100 ns, which is way too slow for an 8 MHz square wave.
You could try to build a level shifter that actively drives both low and high signals with multiple FETs, but it would be easier to just use a level-shifting logic chip. There are level shifters with two supply voltages (e.g., 74LVC1T45), but 3.3 V signals are TTL compatible, so you can use any 5 V buffer with a TTL-compatible input, such as the (SN)74AHCT1G125/MC74VHC1GT125/TC7SET125.
For a healthy 8MHz clock, presumably swinging 0V to 5V, you'll need at least the 3rd harmonic and maybe the 5th harmonic, thus 40MHz frequency response. Invert 40Mhz to get 25nanoSec period, then reduce by 6.28 to 4nanoSecond. That value, 4 nanoSec, is the Drain R*C timeconstant for a healthy signal.
There are Power MOSFET driver ICs that will do this, needing no resistors.
I need to step-up a clock signal of 8 MHz from 3.3V to 5V
There's a good chance that you don't need to do anything. Most devices are TTL level compatible and this means anything over 2 volts is guaranteed to be regarded as a logical 1 and anything below 0.8 volts is regarded as logical 0.
Should your 5 volt input device be a schmitt trigger then some adjustment is called for. At 5 volts, the nominal schmitt trigger thresholds are 3.5 volts and 1.5 volts and, as you can see, this implies a signal amplitude greater than 2 volts peak-to-peak. In this case, capacitively couple the clock to a potential divider that sets the DC level at 2.5 volts. Now the clock will rise up to 4.15 volts and down to 0.85 volts.
