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I am making last minutes changes to USB 2.0 differential pair routing on Atmega32u4 based board. I can't re-route the entire board and/or re-arrange the components. So the picture attached is the best I can do.

One thing I don't like about the current routing is that (from the USB + and - pins at 1), it is using vias (2) and the differential pairs (3) are running below the MCU pins.

I try to keep the USB signals as isolated and simple possible. And running them through vias and under the MCU pins are making me nervous. That said, I have heard USB 2.0 signals are very robust. So I am hoping this is ok.

Please take a look at the screenshot and provide your insight! Will be much appreciated.

USB2.0 on Atmega32u4

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    \$\begingroup\$ It's only USB Full Speed, so it's probably not hyper-critical. Usually it's best to run over solid ground plane. It looks like you've got pretty good matching though so that's something. You'll never know til you try it. \$\endgroup\$ – Daniel Feb 18 '17 at 8:09
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    \$\begingroup\$ If all you've got is a single set of vias, you'll be fine. USB 2.0 is relatively forgiving. You didn't show the rest of the circuit, but as long as the pins that the diff pairs are under don't have any low-noise analog signals on them, it looks fine. \$\endgroup\$ – uint128_t Feb 18 '17 at 17:34
  • \$\begingroup\$ @Daniel The matching is pretty close. I did manage to move the differential pair from the MCU pins. Still no solid ground plane underneath them, but that's the best I can do! \$\endgroup\$ – Adam Lee Feb 19 '17 at 0:58
  • \$\begingroup\$ @uint128_t I actually have another set of vias on the other side. So each differential signal goes through two vias over the length of 3.5 inch long trace. Do you think this can harm the signal quality significantly? \$\endgroup\$ – Adam Lee Feb 19 '17 at 1:03
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    \$\begingroup\$ Two sets of vias and 3.5 in of trace? You'll be fine. Again, USB 2.0 is designed to work with cheap cables, cheap board design, etc. At 480 Mbps, it takes a lot of vias to affect the signal. \$\endgroup\$ – uint128_t Feb 19 '17 at 1:40
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According to this article avoid routing the differential USB signal over the BGA pins

  • Do not place probe or test points on any high-speed differential signal.

  • Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.

  • After BGA breakout, keep high-speed differential signals clear of the SoC because high current transients produced during internal state transitions can be difficult to filter out.

  • When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer. TI does not recommend stripline routing of the high-speed differential signals.

  • Ensure that high-speed differential signals are routed ≥ 90 mils from the edge of the reference plane.

  • Ensure that high-speed differential signals are routed at least 1.5 W (calculated trace-width × 1.5) away from voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are voided.

  • Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission lines.

  • Maximize differential pair-to-pair spacing when possible.

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    \$\begingroup\$ That is a QFP package. \$\endgroup\$ – Daniel Feb 18 '17 at 10:44

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