I've made 4 bit adder circuit using 4008 IC. And the sum output of the two 4 bit numbers from that IC was feed to one BCD to 7 segment decoder (74LS47) so that I can get decimal output. But since I can't diplay numbers over 9, I need two 74LS47 ICs. But what additional circuitry shall be made so that it can stop that overflow over decimal no. 9? And suppose my two binary numbers to be added are 101(5) +101(5) I will get binary output of 1010(10). How can I display this using two BCD to 7 segment decoder ICs?
I had once done this as part of my digital circuits lab. Your problem is that you have a 4-bit no. input (0-15) which needs to be given to 2 74ls47 ics. Say the 4 bit input no is a b c d, inputs of 74ls47 ic for tens place are p1 q1 r1 s1 and that at for units place p2 q2 r2 s2 (Here a and p are MSBs). You can now make a truth table with abcd inputs and corresponding values you wish to get at both the pqrs. Next, based on this table you need to solve the Kmap for each of the 8 variables p1-s2. Each of these variables depends only on the 4 inputs: abcd, So you have to solve 8, 4x4 Kmaps. Looks tedious but all the Kmaps and expressions for pqrs will be quite simple. Quoting from my lab report:
p2=a(c')(b') q2=b(a'+c) r2=ab(c')+(a').c s2=d s1=a.(b+c)
You don't need p1 q1 r1 to display 0-15. Implement this using basic logic gates.
Use hexadecimal. A single hex digit (0-9,A-F) represents one of 16 states, so 4 bits.
This is exactly why hex (and in older times octal, not much anymore) were used. Each digit directly indicates 4 bits (3 for octal). For your own hobby project, and even displaying values in a computing context, you can often use hex directly.
If you have to display decimal values to end users, then use a microcontroller. All this dedicated hardware just to generate 7-segment display patterns for decimal numbers is silly in today's world. A microcontroller can do the binary to decimal conversion, then convert each digit to the corresponding 7-segment display pattern. It can even multiplex multiple digits to reduce the number of connections, and therefore the chip size and routing complexity.