In I2C, why SCK and SDA should be open drain? What will happen if they are not open drain. I am trying to implement I2C communication using bit banging. Should I enable Open drain circuitry of GPIO pins for SCk and SDA? I am asking this may be because I dont know about open drain logic.


I²C is not a strict master-slave protocol (although your circuit might use it this way), but allows multiple masters, and allows slaves to delay transactions by clock stretching.

This means that multiple devices can drive the same signal line at the same time. And if two devices try to drive different levels, the result would be bus contention, which would not only make the actual level undefined, but also would form a short between VCC and GND which could burn out the output transistors of these devices.

In an open-drain system, if one device pulls the bus low while another device lets it float high, the result is a low signal. This is used by the I²C protocol to detect conflicts in a multi-master system, and to let the master detect when a slave pulls the clock low to delay it.

If you have only a single master, and if your slaves do not support clock stretching, you can use a push/pull output for the clock line. But the data line is written and read in the same transaction, so you must never actively drive it to the high level.

  • \$\begingroup\$ if there is only slave on the bus, then also is it required to be open drain? Is Open drain only for resolving the bus contention? \$\endgroup\$ – xyz101 Feb 18 '17 at 18:59
  • \$\begingroup\$ The master controls SCL, but as far as SDA is concerned, reading and writing work symmetrically, so master and slave must be implemented in the same way. \$\endgroup\$ – CL. Feb 18 '17 at 21:03
  • \$\begingroup\$ But is it required, if I2C is implemented using bitbanging, with one slave.As the master knows, when it should release the bus for slave to reply. \$\endgroup\$ – xyz101 Feb 19 '17 at 16:48
  • \$\begingroup\$ How do you ensure that the slave does not drive the line low while you are driving it high? \$\endgroup\$ – CL. Feb 19 '17 at 17:18
  • \$\begingroup\$ Because, master knows on the 9th cycle bus should be released and master also knows when slave is ready to send the data. There's no clock streching. A simple I2C implementation is being thought \$\endgroup\$ – xyz101 Feb 19 '17 at 17:30

Use op open-drain outputs on I2C devices is required to avoid bus contention. Any device must be able to try to transmit at any time without the risk of damaging itself or other parts. Another requirement is the external pull-up resistors (typically 4.7k). A device would check that the data line is high before using the bus. If two more more devices try to transmit by making the data line outputs, but they are both open drain, no damage can happen, only incorrect data.

  • \$\begingroup\$ how does open drain output actually cause the bus to be low, if one is driving the bus HIGH and the other is driving the bus LOW? \$\endgroup\$ – xyz101 Feb 18 '17 at 19:02
  • \$\begingroup\$ It can't be driven high if the output is open-drain, that's the point. it can only be driven low. The resistor is there to pull the line high when none of the outputs are holding the line low. Even if there is only one slave on the bus, usually you still need open-drain outputs, because sometimes the slave will need to respond to the master. If you are doing this purely by bit banging, you might be able to do it without open-drain outputs, but I2C is not nearly as straightforward as something like bit-banging UART or SPI. \$\endgroup\$ – AngeloQ Feb 18 '17 at 19:56

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