I'm designing my first ever circuit for a hobby project. I've a sensor that outputs in mV (1 to 2) and a controller with ADC. The ADC is 16 bits, VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz. Since the sensor voltage that is fed is to the controller is low I'm in a predicament! Should I use a low pass filter or a band pass filter in this application? Do you have a circuit that I can relate to? I've attached an example plot. Any advice is appreciated. Thanks :)
It looks like the sensor may have insufficient signal to noise ratio over the frequency range of valid signals. You also have a secondary problem in that the sensor signal of 1 to 2 mV is way too small for the 0 to 3 V A/D range. That can be solved with amplification.
It looks like your signal period is a bit over 20 s. It's not a sine, so some harmonic content looks to be important. You haven't given response time or frequency range requirements, but let's say anything past 2 Hz is noise.
Since 2 Hz is very slow for any microcontroller, you can use a rough analog low pass filter, sample much faster than you need the data, then low pass filter in the firmware.
For example, let's say you can sample at 10 kHz. That's 100 µs per sample, which is a long time even for cheap and small micros. Two poles of R-C low pass filtering at 500 Hz won't matter to the signal at all, but will squash signals above the aliasing limit of 5 kHz. For example:
The two poles are actually nominally at 480 Hz with these part values. This filter would go between the sensor and the amplifier that drives the A/D input. It's purpose is not make the final filtered signal, but just to ensure that there is no aliasing when the signal is sampled at 10 kHz.
In the micro, you then run a low pass filter that squashes frequencies above 2 Hz. This digital filter can be more complicated if needed, and won't suffer from analog part tolerances. I'd start with two poles of low pass filtering at 2 Hz.
It is unclear from your graph what signal to noise ratio you will get this way, but try that and see. If you substantially reduce frequencies past the valid signal and still don't have enough signal to noise ratio, then you need a better sensor, or you need to reduce the bandwidth requirements.
Using Signal Chain Explorer, with numerous Efield and Hfield aggressors active under the Gargoyles mode, with 159Hz LPF before the single-stage gain, and 1.59Hz after that gain stage, we see 8.8 bits ENOB/55dB SNR. Notice the FOI frequency of interest is 10Hz; this should be 2Hz or 1Hz. (also, click on the topright I/C InterconnectsModel, so EFI/HFI have targets for their fields.)
Reducing FOI (top right) to 1Hz produces 69.6dB SNR
How can we trust predictions of Signal Chain Explorer, regarding interference? Examine this diagram of the PCB trace: 14mm long, 1.5mm above the plane, 1mm wide. The Hfield aggressors couple into the Loop: 14mm*1.5mm; the Efield aggressors couple into the trace area: 14mm*1mm. However, the Efield math needs to account for the HighPassFilter behavior of capacitive charge injection, using the vulnerable node(s) impedances.
Your signal has too much noise to be useful.
I eyeballed a mean signal that might be a high order LPF and although there is correlation in some cycles , not in every cycle. The results are almost meaningless for position sensing.
I suggest there are a few problems that can be improved greatly with much more disclosure on details.
- Provide details on design,sensor,cabling, layout and sources of EMI for improvement on EMI reduction. This includes radiated noise and conducted noise.
- Improvements needed may range from higher gain at sensor, shielding, balancing, and filtering both the noise source and the sensor signal and averaging results.
- Note that motor noise is likely and ADC noise at Fadc=3MHz reduces accuracy on ARMs from 12 bits to <9 bits without quiet mode etc so 1mV is too low a signal
There are lots of free filter design tools if you know what you need. This must be defined 1st.
- gain - Passband (PB) freq. ( eg 1Hz or 10Hz) - PB ripple ( <1dB) - Stopband (SB) freq. ( eg 10 Hz or 100 Hz) - SB reject @ above f (-40dB ) 2nd order is 40dB /decade
eg free from TI Large caps can be scaled down by 100 while R increased x100 so if you use Rail to rail OA's rated for 10K load, you do not need lower values. Also use 1M ~10M max depending on bias offset. This is not a final design just a starting point. If you use single supply 0~3V then use Vcc/2 as your ground ref with Resistors and cap.
You need an amplifier. Your signal is so low that the ADC is having trouble reading. That might be why it just looks like noise. Or it's because you're unshielded. You need to use a shielded coax and maybe balanced cable to a +40dB amp. A simple op amp circuit would be fine but you might get significantly better results if you consider the source impedance of the sensor and select a part that matches that impedance and possibly at the right frequencies. If you post a link to a datasheet for the sensor, you'll get better answers.