The data sheet shows the clock signal hitting 0.1VCC and 0.9VCC. However, the clock signal I sense by probing is only ranging from 1.1V to 2.8V (for 5V VCC). With active oscillators such as these, is it necessary to drop the output across a resistor? Their test setup suggests they only dropped it across a 50pF cap. I was hoping the input capacitance of the MCLK pin would be enough(3pF, data sheet says max is 50pF).
It appears you have excess load on the clock signal at 2.8V for 5V logic.
The Kyocera spec indicate Vo="1" at 0.9Vcc @ 16mA so for Vcc=5V this drop represents 0.1*5V=0.5V @16mA Zout = 0.5V/16mA = 31Ω, which is good.
This means if you also had external clk input with 50Ω terminator which loads your Kyocera output , it should reach 50/(50+31)*5V=3.1V unless reduced by excess capacitive loading. Threshold nom is 2.5V.
You could offer more design details if you want a better answer:
schema, layout, waveforms, probe method, DC Voltage on each DC pin.
- the series R on design kit schematic are DNI but 25 Ω might improve clock symmetry. Pullup/down 100~330 Ω each also might improve integrity instead of 50Ω for ext. clock ( if used), Otherwise look for problems, this is not normal.