# Relationship between Electrostatic Force and Circuit Layout / Dimensions

Super basic question, but I'm struggling to figure out how to word this: In the usual scenario, current in an electrical circuit is induced by some voltage differential (maybe this last term is redundant). The voltage is based on the various electrostatic forces, which are represented as a field. The field doesn't have to stay within the boundaries of the circuit's wire (since it's a field), whereas typically, the current does (I know there are exceptions in cases of high voltage). Does that mean that the layout of the circuit (ie how close the components/wire are placed from each other) could affect it's ability to operate as expected? For example, could you reduce a working circuit to a really small size and find that two different wires are really close together, causing some sort of interaction based on the comingling electrostatic fields? Could this effect inhibit the circuit's proper operation? (Maybe you could inadvertently create something like a primitive capacitor?) Is there a limit to how big/spread out you could make a given circuit?

• Your suspicions are correct. Crosstalk and electrostatic (capacitive) coupling can cause big problems if the circuit layout isn't done correctly. Feb 20, 2017 at 18:33
• These effects are often contributing to EMI-noise, so yeah the layout greatly contributes to the total electrical characteristic of the system. Every trace carrying a time-varying signal can be thought of as an antenna emitting that frequency. Feb 20, 2017 at 19:16

If you scale all dimensions down capacitance drops linearly with scaling: -

If d halves and the dimensions of the plates also halve, then A reduces by 4. Hence capacitance halves for a 2:1 rescaling.

It's a the same for stray inductive coupling too.

• For a single layer PC boards the area is in essence the copper thickness times the trace length and d the distance between traces. Scaling down will not change C. Feb 20, 2017 at 18:38
• @user1831847 the traces will get shorter end-to-end and this will reduce capacitance of course. What scenario do you envisage that I'm clearly not able to see (bearing in mind that the question, as currently posed, does not restrict answers to only considering PCBs)? Feb 20, 2017 at 18:47
• you are right, the PCB traces will get shorter but the distances d as well. No change to C then. Feb 21, 2017 at 4:54

I think the answers posted here are missing the main point of the question: in short, the answer is no, that is, not as you think: the potential in the wires is not due to an electrostatic field in the surrounding space; this is because unlike electrostatic class exercises, the wires creates boundary conditions that restrict the electric field to be very weak in the vicinity of the wires: only the component parallel to the wire plays a role in the displacement of the electrons along the wire, so, by itself, the electric field causing the electron motion does not affect the other wires.

BUT

as pointed out in the previous answers, other effects are playing here: firstly, there is the capacitive effect between the wires and between the other components of the circuit: anything has a self capacitance, and two close wires have also a mutual capacitance. This often create capacitively coupled circuit, much like as if you had put a capacitor between the two wires.

Second, there are also magnetic effects: if your circuit contains a wire that forms a loop, then the current moving in the loop will create a strong magnetic field, that will induce currents in other wires. That is why it is important to avoid loop in circuits (and also because this forms a loop antenna that grasp electromagnetic waves). In fact, even a simple straight wire cause a magnetic field in the surrounding space.

Finally, there are electromagnetic emission effects, that become extremely annoying as frequencies increase. Every wire subject to an AC current of high frequency behaves like an antenna. And any other wire can receive this signal. Here, this is different from the electric field you spoke about in your question, and is related to EM wave theory. An EM wave is a combination of an electric field with a magnetic field propagating in a medium, due to the superposition of the oscillations of infinitesimal electric dipoles.

These subjects are a complicated matter, known as "electromagnetic noise" in the circuits (EMI noise). There are many things to do to reduce the noise (good circuit design, reducing the length of the wires, shielding etc).

The final point: more or less, as far as the frequencies inside your circuit are low, and as far as the circuit is not high precision, you have not to worry with EMI noise: even if your circuit is wired in an awful manner, it will probably work. For precision or high frequency circuits, this is no more true and you have to take EMI noise into account in your design.

Consider wire-over-plate capacitance: Schaums Outline provides formula:

$$Capacitance/meter = 2*pi*E0/ln(2*distance/wireradius)$$

Compare to the parallel-plate formula:

$$Capacitance/meter = E0*Er*PlateWidth/PlateSeparation$$

The wire-over-plate has capacitance decreasing as 1/ln(2*distance) whereas parallel-plate is 1/distance. [The Schaums Outline author warns his formula is not accurate when wire is very close to the plate.]

If you want to tinker with integrated-circuit distances (100micron distance between OpAmps, the IC metallization placed 1micron above "gnd" (nominally substrate), then download the free tool Signal Chain Explorer from the website robustcircuitdesign.com and build yourself a signalchain. Click on the Gargoyles (the magnetic and electric field aggressors), click "update" and watch the SNR change as you edit either (1) the Global Interconnections (click the topright "I/C" button, or (2) the individual TRACES between stages. To see the traces, ensure the topmiddle "Show Interconnects" is clicked. Down in the WIRING WIZARD, you can alter the nominal distances to be silicon-distances, or even sub-atomic.

Here is an example