# what the best way to calculate Rg gate driver for Mosfet

I need to drive a MOSFET IPW90R120C3 from Infineon here the Specification of MOSFET

VDS @ TJ=25°C 900 V
Rdson @ TJ=25°C   : 0.12ohm
Qg = 270nC


Specification of driver IR2110

Isource: 2A
Isink : 2A
VOUT 10 - 20V
ton/off (typ.) 120 & 94 ns
Driver supply : 15V


The switch frequency Fsw= 50KH

what the best way to calculate the resistance Rg to drive proprely the MOSFET ? best regards • Probably include the datasheets of the MOSFETs. – Bradman175 Feb 20 '17 at 22:00
• Datasheet of Mosfet : infineon.com/dgdl/… – user3212448 Feb 20 '17 at 22:06
• I bet it is the maximal gate current. The MOSFET gate is capacitor like, therefore it will sink/source current $I_g=\dfrac{V_g}{R_g+R_{g_{internal}}}$ – Marko Buršič Feb 20 '17 at 22:19
• UPDATE: The maximal current of the gate driver on the picture. – Marko Buršič Feb 20 '17 at 22:24
• @ Marko Buršič, Yes it is the maximal gate current. I searched and read many Application notes from supplier , but did not find a specific answer or a genaralist formula to calculate the correct value for a Rg resistor for a MOSFET's. the right formula must includ the Gate Charge Qg, and the swithing time turn ON - Turn OFF, Or by using the Output voltage slop dVout/dt – user3212448 Feb 20 '17 at 22:29

"best way" comes downto what you are trying to achieve?
Switching is all about charge transfer. You need to transfer 270nC worth of charge in (or out) of the gate region to turn the device on (or off). It is also about charging up the relevant capacitance.

$Q_{gs} \Rightarrow Q_{gd} \Rightarrow Q_g$

The turn on of the device can be split onto two region's

1. Period 1. Time to charge the gate to the threshold. This is the delay and is influenced by the input capacitance $C_{iss}$ (or $C_{gd} + C_{gs}$)
2. Period 2. Time to saturate the device, This is the rise time & is governed by the remaining gate charge.

The actual turn on characteristics (and equally turn-off) is split into three regions, (charging to threshold, charging through the millar, charging to saturation) but without a detailed charge plot of the millar plateau it is more of a talking point

$\Delta V = (V_{end} - V_{start})(1 - \frac{1}{e^{\frac{t}{\tau}}})$

$t = RC ln(1 - \frac{\Delta V}{ V_{end} - V_{start}})$

Period 1

$V_{gg}$ is 10V = $V_{end}$

$V_{0}$ is 0V = $V_{start}$

$V_{th}$ is 3V = $\Delta V$

C = 6.8nF (from $C_{iss}$)

From this a 1st pass approximation of $R_g$ can be done based upon a required delay time

Period 2

$V_{gg}$ is 10V = $V_{end}$

$V_{th}$ is 3V = $V_{start}$

$V_{gg} -V_{th}$ is 7V = $\Delta V$

$Q_g$ is 270nC -> $C_g = Q_g/Vg = 27nF$

C = 20.2nF (from $C_g - C_{iss}$)

This will facilitate deriving a gate resistance for a given rise time. This value is of greater importance than delay time.

There are three other considerations with regards to gate drive

Power

$P_{drv} = Q_g f_{in} \Delta V_g$

The faster you want to switch, the more power it will take

Current

$\hat{I_{out}} = \frac{\Delta V_g}{R_{g\_min}}$

The lowest gate resistor is governed by the output current capability of your driver

Stability

$R_{g\_min} = 2 \sqrt(\frac{L_g}{Cg})$

To minimise creating a pierce oscillator, the damping factor associated with the L-C circuit must fulfil the damping condition

• the stability is something new to me , so i got curious , by inductance of the gate is you mean : lead mosfet package and PCB layout , right ?? – ElectronS Feb 24 '17 at 15:16
• yup. The "gate resistance" is all the resistance from the rail to the gate (driver, purpose resistor, traces, chip resistance) and the "gate lead inductance" is the stray inductance due to any leads in the package, traces etc. The number of gate-drive designs that have inadvertently created a pearce oscillator simply because of poor layout and a very low resistor is just silly..,. – JonRB Feb 24 '17 at 15:20
• i get the resistance part and it is straight forward , but the inductance part is a bit difficult to measure , right ? and what are the clues that the gate driver has created a Pearce oscillator ? is ringing on the gate a symptom ? – ElectronS Feb 24 '17 at 20:11

You should look on datasheet of the gate driver circuit, then look for max. current and $R_{ds_{ON}}$, look for internal gate resistance of the MOSFET, too. $$I_g=\dfrac{V_{driver}}{R_{ds_{ON}}+R_g+R_{g_{MOSFET}}}$$

The gate driver you have chosen is not a good fit. The Source/Sink Current is 2A, but if you calculate the Ig based on Turn On Time (90 nS) and required gate electric charge, which is 270 nC: Ig= dQ/dt= 270/90= 3A (at least this 3A is required, I would go for 5A)

The best design solution is explained by @JonRB Thank you for your complete response, but I have some concerns about it:

By using the datasheet parameters, for the first period of Ton (delay), I calculated Rg1=~29 ohms. For the second period, the rise time, you mentioned: Vgg is 10V = Vend Vth is 3V = Vstart Vgg−Vth is 7V = ΔV By substituting these values we get Ln (1-7/7) = Ln (0), which is not defined. If we say: Vgg is 10V = Vend Vth is 0V = Vstart Vgg−Vth is 7V = ΔV Then, we get Rg2=~ 1 ohm. However, this doesn't agree with what you said before: "This will facilitate deriving a gate resistance for a given rise time. This value is of greater importance than delay time." Please let me know where I make a mistake.