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Full disclosure, this is a circuit I've constructed as part of a lab at school, however this isn't a specific question I need to answer in the report, this is something I've observed and can't explain and would to figure out for myself.

We're constructing a phasor effect filter by cascading four all-pass filters and summing this signal with the input signal. The filter imparts a +180 to 0 degree phase shift depending on the input frequency and the location of the pole/zero frequency. If each of the four filter imparts a 45 degree phase shift on an input sinusoid, then the sum of the input and the output of the cascade will be zero (the result of the consecutive filters is a net of 180 degrees of phase shift).

Anyway, to control the pole/zero frequency we're using a JFET, and the main problem I've noticed is that adding the JFET to the circuit creates a DC offset in output which I cannot explain.

Here is the circuit for one of the filters. (R4 and R5 are just a voltage divider to get the gate voltage to the right level).

schematic

simulate this circuit – Schematic created using CircuitLab

I don't have a photo of the scope capture (though I may be able to grab one later), with the control voltage (Vc) tied to ground, which should turn the JFET fully on (with a R_DS_on resistance of about 300 ohms), the output has a positive DC offset. Removing the JFET from the circuit makes it disappear. The offset amplitude seems to have some sort of mild frequency dependence?

If it matters, the op amp we're using is a TL071.

I know I can mitigate this effect by AC coupling each stage, which I may vary well do, but I would like to figure out why this is occurring.

Any insight would be greatly appreciated.

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Is the JFET forward-biased? That gate-channel diode should be OFF.

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  • \$\begingroup\$ That's an interesting thought. The input swings positive and negative, so potentially it is only forward-biased for only positive input voltages (with the gate at 0V)? \$\endgroup\$ – Matt Egan Feb 21 '17 at 6:25
  • \$\begingroup\$ I agree, Vc must be negative and having signal swing across drain-source might result in rectification. You might want to analyse this in a circuit simulator. \$\endgroup\$ – Bimpelrekkie Feb 21 '17 at 7:03

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