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Reading an SPI Flash datasheet, I encountered the concepts of "dual I/O" and "quad I/O". At first I thought that "dual I/O" was synonymous to "full duplex", but then what is "quad I/O"?

What is dual I/O and quad I/O, and how do they compare do duplex and full duplex?

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  • \$\begingroup\$ For example, the Zynq PS (Cortex A9) has a QSPI controller and interfaces on a Zed board to 4-bit SPI (quad-SPI) serial NOR flash. The Spansion S25FL256S \$\endgroup\$ – user50983 Aug 8 '14 at 18:17
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A multi I/O SPI device is capable of supporting increased bandwidth or throughput from a single device. A dual I/O (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices. A quad I/O (four-bit data bus) interface improves throughput four times.

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    \$\begingroup\$ That's not an SPI device -- SPI doesn't use bidirectional pins. \$\endgroup\$ – Ben Voigt Mar 27 '12 at 18:37
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    \$\begingroup\$ SD memory cards support using a 4-bit bus. It's difficult to say they are "not an SPI device" since the same card (at some other time) can use the standard "1-bit" SPI bus. \$\endgroup\$ – davidcary Mar 27 '12 at 19:07
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It means that you have more serial lines that share the same control signals, or put differently, a serial port with more than one data line.

Both dual-I/O and quad-I/O are half duplex (explained at page 10), because in dual-I/O both lines are used in parallel to increase the throughput mantaining the same number of wires, whie in quad-I/O also DQ2 and DQ3 are used as I/O together with DQ0 and DQ1.

Note that dual-I/O mode uses the same number of lines than the normal SPI bus, avoiding the need of additional pins in the uC and dedicated hardware design.

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    \$\begingroup\$ "a serial port with more than one data line" would be called a parallel port. \$\endgroup\$ – immibis Jun 30 '16 at 8:07
  • \$\begingroup\$ @immibis not necessarily, because in a parallel port the two signals must be synchronous to each other, while two serial lines can transmit independent streams that are combined by the receiver \$\endgroup\$ – clabacchio Jun 30 '16 at 8:10
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    \$\begingroup\$ But the clock is shared. Both signals are synchronized to the clock, and transitively, to each other. \$\endgroup\$ – immibis Jun 30 '16 at 8:11
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    \$\begingroup\$ @immibis what I mean is that too be parallel you send two- or four-bit symbols on the two lines, while here you can send two true serial streams in parallel \$\endgroup\$ – clabacchio Jun 30 '16 at 8:14
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That protocol is called SQI (resembling SPI) meaning Serial Quad I/O Protocol. You can sed the adress/command/data trough 4 pins instead of only one (SPI) and receive de data trough the same 4 pins.

Being half or full duplex is a characteristic of a comunication system regardless of the protocol you decide to use (of course some protocols allow full-duplex and some just don't).

Indeed, Dual and Quad I/O are not the same as full-duplex, they are just different protocols you can use (sometimes with the same device). Starting with SPI (I'm assuming that you know what this is) that has 1 pin to send and then receive (meaning that the protocol is half-plex); we then have Dual I/O that uses 2 pins to send and the receive (half-duplex), and finally Quad I/O that uses 4 pins to send and then receive (also half-duplex).

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Nowadays, people called it as SPIFI interface. This is mostly used in Flash interface.

Take a look at LPC18xx datasheet, chapter 21 : SPIFI. Link : http://www.nxp.com/documents/user_manual/UM10430.pdf

1 Bit SPI : Data will on 1 line.

E.g. :- Bit sequence 7 6 5 4 3 2 1 0

2 Bit SPI or Dual SPI : There will be data on 2 line.

E.g. :- Bit sequence

    Line 1 : 7 5 3 1

    Line 2 : 6 4 2 0

4 Bit SPI or Quad SPI : There will be data on 4 line.

E.g. :- Bit sequence

    Line 1 : 7 3

    Line 2 : 6 2

    Line 3 : 5 1

    Line 4 : 4 0
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    \$\begingroup\$ hey, i think you missed to see that the OP has accepted the answer already and also it is a 4 year old question. Your points are already covered too. \$\endgroup\$ – Umar Mar 10 '17 at 5:40
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    \$\begingroup\$ @Umar, to be fair, this answer shows that it is actually called SPIFI and also shows the bit sequences. Both of these things are not covered in other answers. So this is a valid contribution no matter how old the original question. \$\endgroup\$ – stanri May 30 at 13:24
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As noted elsewhere, some flash devices have an option use two or four pins to output data. Another option I've seen on at least one flash chip was to use one pin, but output data on both rising and falling clock edges. This would allow double-speed transfer on a microcontroller which could handle such a data format, without requiring any extra data pins, so four clocks would output each byte of data on one pin. I'm unaware of any controllers that support such a feature, though I'm also unaware of any that support the use of two or four data wires.

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    \$\begingroup\$ The Microchip ATSAMS70 and similar ARM processors support dual and quad SPI to execute code from an external flash memory such as the Micron N25Q series flash chips, which also support dual/quad SPI. \$\endgroup\$ – user4574 Jul 28 '17 at 20:40

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