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From what I understand one column and row pairing corresponds to 64 bits from the DRAM chip, but this makes me think that one would then incur the CAS Latency (~18 clock cycles in DDR4) for EVERY transfer. I feel like this is obviously not the case or else DRAM would be severely limited by the CAS delay and not the available bandwidth. Thanks for the help!

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    \$\begingroup\$ Isn't it totally up to the specific chip? \$\endgroup\$ – Eugene Sh. Feb 21 '17 at 14:46
  • \$\begingroup\$ With the right device (one that has page-mode support) you can get 256 bits from a CAS access. \$\endgroup\$ – Brian Drummond Feb 21 '17 at 15:01
  • \$\begingroup\$ Don't forget that DDR chips have multiple banks internally, which means that you can interleave operations on individual banks to keep the I/O bandwidth filled up, even if any single bank can't do it on its own. This is what we normally do in high-bandwidth video systems, where the problem is somewhat simplified because nearly all of the accesses are sequential anyway. \$\endgroup\$ – Dave Tweed Feb 21 '17 at 15:19
  • \$\begingroup\$ Great point Dave. Can you expand upon what you mean by multiple "banks"? I am familiar with the concept of ranks in memory systems. Are they the same? \$\endgroup\$ – Erik Anderson Feb 21 '17 at 15:32
  • \$\begingroup\$ I don't know what a "rank" is in this context. A typical DDR chip has 4 banks that operate essentially independently of each other, except that they share a common set of input (address and command) and I/O (data) buses. They can usually transfer up to 8 words of data in a DDR burst. You can initiate a burst transfer on bank 0, and while that is happening internally and on the data bus, you can initiate a burst on bank 1 using the command and address buses, and so on. By the time the burst on bank 3 has been started, bank 0 is now ready for a new operation. \$\endgroup\$ – Dave Tweed Feb 21 '17 at 17:54
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How many bits depends upon the width of the memory chip, you can always put more in parallel to get more data at the same time. So each access cycle is whatever the width of the chip is.

It can vary but generally you can access multiple row addresses without having to set the column again as long as it's the same.

If the rows are all in a block then you can be even faster and do a burst where the chip itself auto increments the row address internally.

In a PC (my knowledge here is out of date here so apologies if it's changed since) the DRAM is always accessed in bursts of 4 cycles, each burst has a fully qualified address with both CAS and RAS set. However other memory controllers can act very differently and can make better use of the potential speed benefits depending upon their application.

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  • \$\begingroup\$ In a x86_64 PC the L2 cache line size is 64bytes so this is the natural size in which you want to access (reading) any higher level ram (plus maybe ECC bits) \$\endgroup\$ – PlasmaHH Feb 21 '17 at 14:57
  • \$\begingroup\$ DDR4 is 64 bits wide which would imply that if you are required to fit the memory in pairs one read is 128 bits and it would take a burst of 4 cycles to fill a cache line. So that seems to tie up nicely. \$\endgroup\$ – Andrew Feb 21 '17 at 15:01
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    \$\begingroup\$ Thanks for the responses. Does anyone know of any good reading material that might have this same information or simply lots of basic things about SDRAM? Preferably something reputable that I could cite in an informal presentation. \$\endgroup\$ – Erik Anderson Feb 21 '17 at 16:46

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