From what I understand one column and row pairing corresponds to 64 bits from the DRAM chip, but this makes me think that one would then incur the CAS Latency (~18 clock cycles in DDR4) for EVERY transfer. I feel like this is obviously not the case or else DRAM would be severely limited by the CAS delay and not the available bandwidth. Thanks for the help!
How many bits depends upon the width of the memory chip, you can always put more in parallel to get more data at the same time. So each access cycle is whatever the width of the chip is.
It can vary but generally you can access multiple row addresses without having to set the column again as long as it's the same.
If the rows are all in a block then you can be even faster and do a burst where the chip itself auto increments the row address internally.
In a PC (my knowledge here is out of date here so apologies if it's changed since) the DRAM is always accessed in bursts of 4 cycles, each burst has a fully qualified address with both CAS and RAS set. However other memory controllers can act very differently and can make better use of the potential speed benefits depending upon their application.