I'm not quite sure how to generate full signal in a FIFO with fast-write and slow-read. Eg., if f_wr=10*f_rd, when the updated writing pointer is synchronized to reading side using simple methodologies for synchronization from fast clock domain to slow clock domain (e.g., by extending the lifetime of the data in fast clock domain), several data could have been written into the FIFO. In such cases, the full signal is not up-to-date and may cause the data in FIFO be overwritten. What kind of special processing should be taken here?
As I tried to generate an FIFO IP in Xilinx ISE, there's no option to input the parameters of the clocks if I choose not to use built-in FIFO, i.e., it doesn't know which side (write/read) goes faster. How does the IP do such synchronization correctly?