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I'm not quite sure how to generate full signal in a FIFO with fast-write and slow-read. Eg., if f_wr=10*f_rd, when the updated writing pointer is synchronized to reading side using simple methodologies for synchronization from fast clock domain to slow clock domain (e.g., by extending the lifetime of the data in fast clock domain), several data could have been written into the FIFO. In such cases, the full signal is not up-to-date and may cause the data in FIFO be overwritten. What kind of special processing should be taken here?

As I tried to generate an FIFO IP in Xilinx ISE, there's no option to input the parameters of the clocks if I choose not to use built-in FIFO, i.e., it doesn't know which side (write/read) goes faster. How does the IP do such synchronization correctly?

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If the average input and output data rates are fixed and different, then you will overflow or underflow a FIFO eventually. There is no 'processing' you can use to avoid corrupting data.

What a FIFO does is act as a flexible buffer to take up temporary variations in the data arrival and consumption rate. The FIFO has to be deep (long?) enough so that it can store all of the excess data, and a bit more for margin.

If your input and/or output rates are not externally fixed, then you can use the FIFO to control one or the other. A FIFO will have full and empty flags, and the Xilinx ones have programmable 'nearly full' and 'nearly empty' flags as well. These can be fed back to your data source and/or and sink to tell them to wait. The deeper the FIFO, the longer you can allow a difference in input/output rate to persist before having to throttle the faster connection.

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  • \$\begingroup\$ Thank you for the reply. I understand that with different write/read speed, the sender receiver have to pause when the FIFO is full/empty, which is similar to flow control in networks. \$\endgroup\$ – fiedel Feb 22 '17 at 15:11
  • \$\begingroup\$ (Sorry had to put the comment in two due to character count limitation.) My question about Xilinx FIFO core is regarding the generation of full/empty signals. I think the synchronization of wr_ptr and rd_ptr should use different approaches when f_wr and f_rd are different (fast-to-slow domain and slow-to-fast domain), and such information is not required in Xilinx FIFO generator (i.e., it doesn't know which is fast and how faster it is), how can the FIFO synchronize wr_ptr/rd_ptr to the other clock domain and generate full/empty correctly? \$\endgroup\$ – fiedel Feb 22 '17 at 15:13
  • \$\begingroup\$ The information isn't required in the Xilinx generator because it isn't relevant. It doesn't need to know which side is fast or slow, as much as anything, because there isn't a fast and a slow side. Each side operates at the same average. Either side can work faster than the other for short periods. The whole point of a FIFO is that it decouples timing between the two sides. You only need local, that is 'this side' timing and synchronisation for your accesses, while ignoring the other side totally. Full empty flags just come out with local timing, correctly, doesn't matter what other side does \$\endgroup\$ – Neil_UK Feb 22 '17 at 16:41

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