1
\$\begingroup\$

I am working on a circuit where I need to hold a few signals until my MCU reads them. Basically the MCU would read these lines at regular intervals (minutes? hours?) and if a line changed state at any stage during this time, it has to be recorded. I am opting for an SR latch, to be cleared by the MCU once the read has been completed.

In this scenario a common reset channel on the IC would help maximizing the numbers of available latches in the same footprint (and make the circuit more elegant and simple). I have found a very elusive 74118/19 (possibly NOR vs NAND). However is practically impossible to find good supply of it and even a datasheet.

Question: Do anybody have an idea of an IC that offers this capability (SR with common Reset)?

Backup question (maybe deserving its own question): Any suggestion on how to implement this otherwise? Looks like an SR is my only choice here, but my brain is just a drop of the ocean.

Thank you all for your help!

EDIT – to clarify a few points in the design: CHEAP AND SIMPLE DESIGN This is meant to be a quick, cheap and low complexity design. The most complex part (by design) is planned to be the MCU. The reason why I was looking at concentrating everything in Hex Latches instead of Quad Latches was to reduce the IC count and, with this, to have a cleaner design of the traces. As far as possible I want to keep it digital and without any high frequency line anywhere (or, better said, well confined in their own "realm": MCU, comms module and voltage regulation sections).

MCU DEEP SLEEP VS INTERRUPTS I'd rather not give too much confidence at these MCU interrupts management. On top of that, when I will get into power-optimization for the MCU I may end up having to choose between keeping the interrupts alive or saving power. I want to keep it flexible, both capability and power-usage wise and this requires balance.

\$\endgroup\$
6
  • \$\begingroup\$ nobody needs this chip any more and you can do similar task with with a D FF in CMOS and gates however the CMOS JK FF is CD4027B. But you can make an SR latch with 2 NAND gates allaboutcircuits.com/textbook/digital/chpt-10/s-r-latch \$\endgroup\$
    – D.A.S.
    Commented Feb 23, 2017 at 6:54
  • \$\begingroup\$ I am nobody! Thanks for the reply. Yeah, looked at the D and JK logic, but that would require providing clock and wouldn't be an "unattended" design as I plan to implement. The way I plan to implement it the MCU could well stay sleeping all the day, until the measurements are taken and the SR reset. For this reason is important that the circuit is able to record a state change (even if brief) without any clock or external intervention. Can't yet wrap my head around applying a D or JK that way. \$\endgroup\$
    – Alessandro L
    Commented Feb 23, 2017 at 8:25
  • 1
    \$\begingroup\$ Is there a reason why you have to use the fewest ICs? As has been said, you can make this function from more 74HCT-etc gates. You could use a tiny low-power CPLD like a Microsemi IGLOO if that fits your situation \$\endgroup\$
    – TonyM
    Commented Feb 23, 2017 at 11:34
  • \$\begingroup\$ While not the ideal for the approach here (simple, cheap and reliable circuit, with only the MCU as "critical complexity"), I believe that your comment may deserve an answer by itself for posterity. I may have to look at CPLD as an option should I plan to further evolve this circuit anyway. But you all know how it works...you start with an LED and a push button and end up with a Zero-point generator in the garage... \$\endgroup\$
    – Alessandro L
    Commented Feb 24, 2017 at 0:42
  • 1
    \$\begingroup\$ I think you need to re-evaluate how much power is required by "keeping the interrupts alive". On processors such as the Atmel AVR that power is in the single microamp region - the clock doesn't need to be running. Look for "Wake-up on pin change", not interrupt. \$\endgroup\$
    – Kevin White
    Commented Feb 24, 2017 at 1:21

3 Answers 3

Reset to default
1
\$\begingroup\$

You may be looking for this:

CD4043/CD4044 3-state SR latch with common enable.

SR latch logic diagram

You might way to use the common enable in the CD4044 to implement the solution you're looking for. Connect all 4 R inputs to Vcc (HIGH), then use E as a common reset. For this to work you need a pull-down resistor on every output. Some MCUs inputs can be configured with internal pull-ups/downs, so you might be able to do this with no additional parts.

Most MCUs inputs can't be configured with internal pull-downs, only with pull-ups. So you may then want to consider another alternative. Use CD4043 instead of CD4044, then connect all 4 R inputs to GND (LOW) and use E as an active low common reset. You will then need pull-ups on every output instead of pull-downs, so just use the pull-ups of the MCU inputs by configuring it accordingly.

Why does this work?

If you look at the truth table of CD4044:

  1. When E is HIGH it's equivalent to set all 4 R inputs to HIGH (= you get the same output from either E or R).
  2. When E is LOW all the outputs will be in high-impedance (open circuit) and the pull-downs of the MCU will force a LOW on them regardless of the S inputs (= it effectively acts as a reset).

You can derive a similar deduction for CD4043.

\$\endgroup\$
8
  • \$\begingroup\$ Hi, thanks for the reply! The CD4044 is indeed the one I have in the design now. The shortcoming is that I have 4 separate resets, while ideally I would need only one. While this is not a huge problem to solve and still match my requirements, the resulting design is not as clear as it would be with a single Reset and the density is lower, requiring me to use more ICs. \$\endgroup\$
    – Alessandro L
    Commented Feb 23, 2017 at 8:27
  • \$\begingroup\$ SN74118N simply has all of its reset inputs internally connected. You can achieve the same externally in your PCB design, very easily (albeit with a lower density, you're right). Any way, take into account that the SN7118N has been obsolete for 25 years, its not a good idea to even consider that part for a new design. Sourcing it could be really troublesome. \$\endgroup\$
    – Enric Blanco
    Commented Feb 23, 2017 at 8:56
  • \$\begingroup\$ OTOH, you might way to use the common enable in the CD4044 to implement the solution you're looking for. Connect all 4 R inputs to Vcc (HIGH), then use E as a common reset. For this to work you need a pull-down resistor on every output. Some MCUs inputs can be configured with internal pull-ups/downs, so you might be able to do this with no additional parts. \$\endgroup\$
    – Enric Blanco
    Commented Feb 23, 2017 at 9:13
  • \$\begingroup\$ Following up my previous comment: most MCUs inputs can't be configured with internal pull-downs, only with pull-ups. So you may then want to consider another alternative. Use CD4043 instead of CD4044, then connect all 4 R inputs to GND (LOW) and use E as an active low common reset. You will then need pull-ups on every output instead of pull-downs, so just use the pull-ups of the MCU inputs by configuring it accordingly. \$\endgroup\$
    – Enric Blanco
    Commented Feb 23, 2017 at 9:23
  • \$\begingroup\$ Thanks Enric! I have toyed briefly with the possibility to use the Enable line, but was not sure if it would have cleared the latched states. After all it looks to act just as a signal gate AFTER the latches. Path-wise, the design difference wouldn't look enormous, but would still be an improvement: I would spare the fixed via to the enable (having it routed to the MCU and used to control the reset AND the enable itself) and would have all the resets linked together in a clean way. However the doubt stand. Is the enable line capable of effectively "resetting" the latches? \$\endgroup\$
    – Alessandro L
    Commented Feb 23, 2017 at 10:08
1
\$\begingroup\$

Any suggestion on how to implement this otherwise?

if you already have a mcu here why would you need a flip flop? the state changes on those lines can trigger an external interrupt on the mcu and you don't need to worry about missing a beat from polling.

\$\endgroup\$
3
  • \$\begingroup\$ See line 1 of the question, it suggests the OP's considered that. Their later comment says the MCU would be sleeping, before you posted your 'answer'. \$\endgroup\$
    – TonyM
    Commented Feb 23, 2017 at 11:29
  • \$\begingroup\$ Given the available info, this is probably the correct answer. A state change on the inputs would wake the MCU - whereupon it reads the inputs and then goes back to sleep. There's a good chance that quiescent current added to the system by an extra logic IC would be greater than the current consumed by the MCU waking up and executing a handful of instructions. \$\endgroup\$
    – brhans
    Commented Feb 23, 2017 at 15:06
  • \$\begingroup\$ I would disagree, but I may be missing the picture here. The MCU uses something in the order of mA (about 40-60mA now, without cuts or optimizations). Even assuming that I manage to cut everything off to reduce its hunger, while keeping a few interrupts alive and memory alive, I am well possibly still looking at power consumption well above the expected sub1μA (quiescent current) of the currently selected CD4044. I know it will likely be just for a few milliseconds, but still it may not be worth the risk/efforts if the figures ends up close. \$\endgroup\$
    – Alessandro L
    Commented Feb 24, 2017 at 1:11
1
\$\begingroup\$

I have never heard of a 74118/19 but I found an obsolete part datasheet for a dual JK TTL 74118.

How about a quad RS latch 74LS279 or 74HC279? enter image description here

Historical anecdotes on my other uses for RS latches.

Once I had a SCADA telemetry design with several low bandwidth (500Hz) DC motor current signals and I didn't need to digitize it and consume whole synchronous channels BW. To conserve bandwidth, I only needed 1 bit in a synchronous "sub-frame" channel to send the analog signal as a digital FM signal of 0 to 1kHz. ( like going to sleep for your system) Otherwise without an RS latch it might miss the 1 shot pulse or worse cause ALIASING (read inter-modulation or beat freq. effect) using the RS latch. ( so I had to invent a linear VCO 0~1kHz ( 40 yrs ago) which turned to be a simple analog sol'n with a 1 shot IC but then I could send 0 to 1kHz asynchronous pulses on a synch. telemetry data channel as 1 bit in a word using a simple RS latch to get rid of aliasing and sampling the logic signal could be anywhere from zero ( like sleep) to equal the sampling rate of 1kHz with a 1us pulse.

Never say you are nobody! You matter to me! +1 to anyone who likes the anecdote.

\$\endgroup\$
2
  • \$\begingroup\$ Comments like these are one of the many reasons for which I regret skipping all the theory in the electronic classes and being in the first line only when there was the risk to toast stuff. Just out of curiosity, you had to have multiple 0~1KHz signals, one for each motor, right? I would probably need to contemplate it for quite some time to fully grasp it. But I guess that the restrictions were far more...restrictive...40 years ago! \$\endgroup\$
    – Alessandro L
    Commented Feb 24, 2017 at 1:20
  • \$\begingroup\$ I had a sync. telemetry design with 4 ch12bit ADC with a 12MHz data rate and only a few spare bits but I wanted to send motor drive current feedback to the remote controller for the probe drive, so I sent it as serial PFM data using the SR latch to a status bit in the subframe. We could design anything back then, just fewer choices of chips, like I had to design my own discrete SSI CMOS UART PCB for an MC6800 which also scanned 96 buttons with 96 indicators. No system this complex has shown up on this site. \$\endgroup\$
    – D.A.S.
    Commented Feb 24, 2017 at 3:19

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.