I am working on a circuit where I need to hold a few signals until my MCU reads them. Basically the MCU would read these lines at regular intervals (minutes? hours?) and if a line changed state at any stage during this time, it has to be recorded. I am opting for an SR latch, to be cleared by the MCU once the read has been completed.
In this scenario a common reset channel on the IC would help maximizing the numbers of available latches in the same footprint (and make the circuit more elegant and simple). I have found a very elusive 74118/19 (possibly NOR vs NAND). However is practically impossible to find good supply of it and even a datasheet.
Question: Do anybody have an idea of an IC that offers this capability (SR with common Reset)?
Backup question (maybe deserving its own question): Any suggestion on how to implement this otherwise? Looks like an SR is my only choice here, but my brain is just a drop of the ocean.
Thank you all for your help!
EDIT – to clarify a few points in the design: CHEAP AND SIMPLE DESIGN This is meant to be a quick, cheap and low complexity design. The most complex part (by design) is planned to be the MCU. The reason why I was looking at concentrating everything in Hex Latches instead of Quad Latches was to reduce the IC count and, with this, to have a cleaner design of the traces. As far as possible I want to keep it digital and without any high frequency line anywhere (or, better said, well confined in their own "realm": MCU, comms module and voltage regulation sections).
MCU DEEP SLEEP VS INTERRUPTS I'd rather not give too much confidence at these MCU interrupts management. On top of that, when I will get into power-optimization for the MCU I may end up having to choose between keeping the interrupts alive or saving power. I want to keep it flexible, both capability and power-usage wise and this requires balance.